Underfill Flow Barriers for Tight Die Spacing in Semiconductor Packages
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Solution Overview
Problem
Current underfill material technologies face challenges in achieving reduced die-to-die spacing in semiconductor packages, particularly in high-performance computing and high bandwidth memory applications, where the epoxy fillet width can prevent memory die attachment and lead to voids during the underfill process.
Innovation Solution
The use of patterned barriers, such as copper traces or trenches, to control the flow of underfill material and reduce epoxy fillet width, allowing for precise modulation of underfill geometry and preventing interference with die placement, achieved through substrate patterning and laser ablation techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional underfill material technology is used, then the underfill process is simple, but the epoxy fillet width is too large to allow reduced die-to-die spacing
Solution Approach 1:
A barrier structure is introduced as an intermediary element between the underfill material and the die. This barrier structure mediates the interaction by controlling the flow path of the underfill material, preventing it from forming excessive fillets that would increase die-to-die spacing, thereby enabling reduced spacing while maintaining proper underfill placement.
Solution Approach 2:
The invention changes the physical parameters of the underfill material flow by introducing a barrier structure that alters the flow dynamics. This modifies the fillet formation process, controlling the epoxy fillet width to be within acceptable limits and enabling reduced die-to-die spacing while maintaining manufacturing feasibility.
2Reliability
If underfill material flows freely, then the underfill process is simple, but voids form during the underfill process
Solution Approach 1:
The barrier structure serves as a mediator that controls underfill material flow, guiding it to flow uniformly beneath the die without forming voids. By intermediating the flow path, it prevents trapped air pockets while maintaining a relatively simple overall process.
Solution Approach 2:
The barrier structure is pre-formed on the substrate before the underfill process. This preliminary action establishes controlled flow paths that guide the underfill material during dispensing, preventing void formation from the outset rather than requiring complex post-processing steps.
3Length of moving object
If barrier structures are added to control underfill flow, then die-to-die spacing is reduced, but the package complexity increases
Solution Approach 1:
Instead of modifying the entire package structure, the invention applies barrier structures only in specific local areas where underfill flow control is needed. This localized approach reduces die-to-die spacing where critical while maintaining overall package simplicity in non-critical areas.
Solution Approach 2:
The barrier structure is segmented into discrete features (such as trenches or traces) rather than a continuous complex structure. This segmentation allows effective flow control for reduced die-to-die spacing while keeping the overall package structure relatively simple and manufacturable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables die-to-die spacing as low as 100 microns, improving the reliability of semiconductor packages by preventing voids and ensuring proper attachment, while maintaining a thin packaging profile and low warpage.
Implementation Method 1
achieved through substrate patterning and laser ablation techniques
Implementation Method 2
patterned barriers, such as copper traces or trenches
Implementation Method 3
epoxy fillet width can prevent memory die attachment
Data Source
AI summary
Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.