Underfill Package Structure With Recessed Substrate for Void Reduction
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Solution Overview
Problem
New packaging technologies for semiconductor dies face manufacturing challenges due to the need for smaller, more integrated package structures that provide effective protection and connection interfaces while maintaining reliability and performance.
Innovation Solution
A package structure is formed with a redistribution structure, underfill material, and protective layer to surround and protect chip structures, and a recess is formed in the circuit substrate to reduce package height and enhance underfill material flow, reducing void formation and improving protection and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the package structure is made smaller to reduce space occupation, then the package height and area are reduced, but the manufacturing complexity and difficulty increase
Solution Approach 1:
The package structure is divided into multiple functional layers including substrate, underfill material, semiconductor die, and protective encapsulant. This segmentation allows each layer to be optimized independently for manufacturing while achieving compact overall dimensions.
Solution Approach 2:
The semiconductor die is embedded within the underfill material which is itself contained within the protective encapsulant layer. This nested arrangement maximizes space utilization and reduces package height while maintaining structural integrity for manufacturing.
2Productivity
If the package structure is made more integrated to increase functional density, then the number of interconnected devices per chip area increases, but the reliability and protection requirements become more challenging
Solution Approach 1:
The package employs composite material structure with underfill material providing mechanical support and stress relief, while the protective encapsulant offers environmental protection. This composite approach enables high functional density while maintaining reliability through material property optimization.
Solution Approach 2:
The underfill material is applied before final encapsulation to provide stress relief and protection to the semiconductor die interconnections. This preliminary cushioning prevents reliability issues from thermal and mechanical stresses in high-density integrated packages.
3Reliability
If underfill material is used to improve protection and reduce voids, then the reliability increases, but the manufacturing process complexity increases
Solution Approach 1:
The underfill material is applied in a controlled manner before die attachment, allowing it to spread and fill voids proactively. This preliminary action ensures complete coverage and eliminates air pockets before subsequent manufacturing steps, improving reliability without requiring complex post-processing.
Solution Approach 2:
The underfill material replacement process uses controlled dispensing and spreading mechanisms rather than complex mechanical assembly. This substitution simplifies the manufacturing process while ensuring proper underfill distribution and void elimination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability and performance of semiconductor packages by ensuring effective underfill material distribution and protection, reducing voids, and allowing for more compact and efficient integration of semiconductor dies.
Implementation Method 1
a recess is formed in the circuit substrate to reduce package height and enhance underfill material flow
Data Source
AI summary
A package structure is provided. The package structure includes a substrate having interior sidewalls forming a recess. The interior sidewalls have an upper sidewall and a lower sidewall, and the upper sidewall and the lower sidewall have different slopes. The package structure also includes a chip-containing structure over the substrate. A component of the chip-containing structure is partially or completely surrounded by the interior sidewalls. The chip-containing structure has a redistribution structure and a chip structure, and the component and the chip structure are disposed over opposite surfaces of the redistribution structure. The redistribution structure has multiple polymer-containing layers and multiple conductive features.


