Semiconductor Underfill Stencil Application and Tip Cleaning
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Solution Overview
Problem
Conventional semiconductor device packaging methods, such as wafer level underfill (WLUF) and capillary underfill (CUF), face issues with entrapped underfill material causing electrical resistance and bond joint integrity issues, while individual underfill application in CUF increases manufacturing time and cost, and reduces reliability due to voids in the underfill material.
Innovation Solution
A method involving a stencil with blocked and open regions is used to apply underfill material on a semiconductor wafer, ensuring conductive elements are partially exposed and free of entrapped material, followed by planarization or plasma removal to maintain the underfill's thickness and integrity, allowing for efficient bonding without entrapped underfill.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer level underfill (WLUF) method is used to apply underfill material over the entire semiconductor wafer, then manufacturing efficiency is improved and cost is reduced, but entrapped underfill material causes electrical resistance and bond joint integrity issues
Solution Approach 1:
The patent segments the underfill application process into two distinct stages: (1) wafer-level application where underfill is deposited across the entire wafer surface, and (2) post-singulation cleaning where entrapped underfill is removed from conductive elements. This segmentation allows the benefits of bulk application to be retained while eliminating the harmful effects of entrapped material through a subsequent targeted removal step.
Solution Approach 2:
The patent applies underfill material to the semiconductor wafer before singulation in advance, allowing the underfill to be positioned and初步 bonded. The harmful entrapped material is then removed in a preliminary cleaning step before final bonding occurs. This preliminary action sequence enables efficient bulk application while preventing contamination of electrical connections.
2Reliability
If capillary underfill (CUF) method is used to individually fill gaps under flip-chips, then electrical connections are free of underfill material, but manufacturing time and cost increase
Solution Approach 1:
The patent merges the advantages of both WLUF and CUF methods by combining wafer-level bulk application (which provides efficiency) with post-singulation cleaning (which ensures connection purity). This hybrid approach achieves the reliability of individual underfill application while maintaining the productivity benefits of wafer-level processing.
3Manufacturing precision
If underfill material is applied to cover conductive elements, then complete coverage is achieved, but entrapped underfill material weakens bond joint integrity
Solution Approach 1:
The patent extracts the harmful entrapped underfill material from conductive elements through a dedicated cleaning step performed after wafer-level application and before final bonding. This extraction process removes the contaminant that would otherwise compromise bond joint integrity, while preserving the beneficial coverage and support provided by the underfill material in the gap regions.
Solution Approach 2:
The patent converts the harmful effect of entrapped underfill into a beneficial process by using the same underfill material's flow properties during cleaning to actively remove itself from critical areas. The material that initially causes problems is utilized in the cleaning process to self-remove from conductive elements, transforming a defect into a solution mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures electrical interconnections are substantially free of entrapped underfill material, enhancing bond joint integrity, reducing manufacturing time and cost, and improving the reliability and performance of semiconductor device packages.
Implementation Method 1
A method involving a stencil with blocked and open regions is used to apply underfill material on a semiconductor wafer, ensuring conductive elements are partially exposed and free of entrapped material
Implementation Method 2
followed by planarization or plasma removal to maintain the underfill's thickness and integrity
Implementation Method 3
followed by planarization or plasma removal to maintain the underfill's thickness and integrity
Implementation Method 4
The WLUF material 30 melts and flows responsive to the application of heat during the bonding process to fill the gap between the flip-chip 11 and the substrate 40
Implementation Method 5
Liquid, relatively low-viscosity dielectric underfill material is then introduced into a gap between the flip-chip and the substrate along one or more edges of the substrate and the flip-chip and is drawn into the gap by wetting of the substrate and flip-chip surfaces and capillary attraction
Implementation Method 6
Liquid, relatively low-viscosity dielectric underfill material is then introduced into a gap between the flip-chip and the substrate along one or more edges of the substrate and the flip-chip and is drawn into the gap by wetting of the substrate and flip-chip surfaces and capillary attraction
Data Source
AI summary
Methods for forming semiconductor device packages include applying an underfill material over a semiconductor wafer including conductive elements such that an average thickness of the underfill material is at least about 80% of an average height of the conductive elements and each conductive element is covered by underfill material. Underfill material covering tips of conductive elements is removed. Other methods include positioning a stencil over a semiconductor wafer and applying an underfill material to a major surface of the semiconductor wafer through the stencil. Additional methods include aligning and associating conductive elements having a surface substantially free of underfill material with bond pads of a substrate, melting and flowing the underfill material, and heating the conductive elements and underfill material to melt tip portions of the conductive elements and cure the underfill material.