Underground DRAM Bit Line Layout for Low Capacitance Sensing

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional DRAM cell designs face challenges in reducing the total capacitance of bit lines, which limits the number of DRAM cells that can be connected to a bit line, necessitating an improvement in semiconductor memory structures.

Innovation Solution

The proposed semiconductor memory structure incorporates an underground bit line design isolated from the semiconductor substrate by different isolating materials, reducing the capacitance per DRAM cell to less than 20×10−3 fF, with specific implementations achieving capacitances as low as 10×10−3 fF to 14 fF, and includes a sense amplifier coupled to the bit line.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional DRAM cell designs are used with bit lines connected to multiple DRAM cells, then the memory capacity and connectivity are improved, but the total capacitance of the bit line increases, limiting the number of cells that can be connected

Engineering Contradiction:

Improvenumber of DRAM cells connected to bit lineVSAvoidbit line capacitance

Core Design Contradiction:

Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The bit line is moved from the conventional planar configuration to an underground configuration, extending it in the vertical dimension below the semiconductor substrate. This dimensional change allows the bit line to be isolated from substrate capacitance while maintaining connectivity to multiple DRAM cells, reducing the capacitance per cell to less than 20×10−3 fF

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Isolation structures (insulating materials) are introduced as intermediaries between the underground bit line and the semiconductor substrate. These isolation structures prevent direct capacitive coupling between the bit line and substrate, significantly reducing the total bit line capacitance and enabling connection to a larger number of DRAM cells

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12417798B2Semiconductor memory structure

Publication Date: 2025.09.16 INVENTION & COLLABORATION LAB PTE LTD

AI summary

A semiconductor memory structure includes a plurality of DRAM cells, a bit line, and a sense amplifier. Each DRAM cell includes an access transistor and a storage capacitor. The bit line has a first terminal extended along the plurality of DRAM cells to a second terminal, and the bit line is coupled to each access transistor of the plurality of DRAM cells. The sense amplifier is coupled to the first terminal of the bit line. A capacitance of the bit line per DRAM cell is lower than 20×10−3 fF.