Underground STI Interconnect Layout for Dense, Cooler Semiconductor Circuits
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Solution Overview
Problem
Conventional semiconductor circuits face challenges in reducing area, power consumption, and noise due to misaligned contact holes and limited heat dissipation, which hinder the integration and performance of transistors as technology nodes shrink.
Innovation Solution
Incorporation of underground interconnection (UGI) structures within shallow trench isolation (STI) regions to form a mid-side signal and heat dissipation network, using conductive materials like tungsten and titanium nitride for signal delivery and high thermal conductivity materials for heat dissipation, with through semiconductor vias (TSV) for efficient backside signal and heat transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional conductive interconnections with contact holes are used to connect transistors, then signal transfer among gate, source and drain regions is facilitated, but area increases due to photolithographic misalignment requiring larger diffusion areas
Solution Approach 1:
The patent introduces underground interconnection lines positioned beneath the transistor active areas, moving the interconnection function from the planar surface dimension to the vertical subsurface dimension. This allows signal routing without occupying additional diffusion area on the chip surface, effectively decoupling interconnection area from active device area.
Solution Approach 2:
The patent employs shallow trench isolation regions as intermediary structures that host the underground interconnection lines. These isolation regions serve dual purposes: providing electrical isolation between adjacent transistor regions and accommodating the underground interconnection infrastructure, thereby eliminating the need for separate contact hole structures.
2Ease of manufacture
If conventional conductive interconnections with numerous contact holes are used, then transistors can be connected, but power consumption increases due to larger capacitances from increased diffusion areas
Solution Approach 1:
By relocating interconnections to the underground subsurface layer, the patent reduces the overlapping area between interconnection structures and active transistor regions. This dimensional separation minimizes parasitic capacitances, thereby reducing the energy required to charge and discharge these capacitances during switching operations.
3Ease of manufacture
If conventional conductive interconnections are used, then transistors can be connected, but noise increases due to larger diffusion areas and capacitances
Solution Approach 1:
The patent extracts the interconnection function from the surface level and places it in the underground subsurface region. This separation removes the interconnection structures from proximity to sensitive transistor regions, thereby eliminating the source of capacitive coupling noise that would otherwise interfere with signal integrity.
4Productivity
If transistor dimensions are scaled down to increase integration density, then more transistors can be integrated, but heat dissipation capability deteriorates due to increased oxide coverage percentage
Solution Approach 1:
The patent segments the shallow trench isolation regions into multiple zones: some regions contain underground interconnection lines while other regions are dedicated to heat dissipation functions. This segmentation allows simultaneous optimization of signal routing and thermal management without interference between the two functions.
Solution Approach 2:
The patent designs the underground interconnection structure to serve multiple functions: electrical signal routing, thermal conduction pathways, and mechanical stress management. The same subsurface infrastructure that carries signals also acts as heat sinks and thermal conduction channels, eliminating the need for separate heat dissipation structures.
5Speed
If higher power is applied to accelerate transistor performance, then transistor speed improves, but die temperature increases adversely due to current limited heat-dissipation capability
Solution Approach 1:
The underground interconnection lines act as thermal intermediaries, providing dedicated heat conduction pathways from hot transistor regions to cooler substrate areas. This intermediary thermal pathway enables efficient heat removal without requiring increased power dissipation, allowing higher operating speeds without proportional temperature increases.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
UGI structures enhance signal delivery and heat dissipation, reducing misalignment issues and improving integrated circuit performance by providing a more efficient power and data transmission pathway while effectively managing heat generation.
Implementation Method 1
a first underground interconnection line within the first STI region and positioned under the original semiconductor surface, and a first underground interconnection pad electrically coupled to the first underground interconnection line
Implementation Method 2
a through semiconductor via (TSV) extending from a bottom surface of the first underground interconnection pad to a backside surface of the semiconductor substrate, wherein the TSV is electrically connected to the first underground interconnection pad
Implementation Method 3
using conductive materials like tungsten and titanium nitride for signal delivery and high thermal conductivity materials for heat dissipation
Data Source
Figure 1
Figure 2A
Figure 2B~2C
AI summary
Semiconductor circuit structures are provided. The semiconductor circuit structure includes a semiconductor substrate with an original semiconductor surface, a set of transistors formed based on the semiconductor substrate, a first STI region neighboring the set of transistors and extending along a first direction, a big STI region remote from the set of transistors, a first underground interconnection line within the first STI region and positioned under the original semiconductor surface, and a first underground interconnection pad electrically coupled to the first underground interconnection line. Each transistor includes a gate structure, a first conductive region, and a second conductive region. The first underground interconnection line extends along the first direction. The first underground interconnection pad is positioned within the big STI region and under the original semiconductor surface. A width of the first underground interconnection pad is greater than a width of the first underground interconnection line.