Underground STI Interconnect Layout for Low-Capacitance Power Delivery
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Solution Overview
Problem
Current integrated circuits face challenges in reducing area, power consumption, and noise due to the need for large diffusion areas and significant photolithographic misalignment in connecting metal wires to transistors, which increases capacitance and limits further scaling and performance improvement.
Innovation Solution
The implementation of underground interconnection lines within shallow trench isolation regions of semiconductor substrates for power and signal delivery, which reduces the need for surface area and minimizes misalignment by using connecting plugs and vias to connect transistors directly to these lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal wires are connected to transistors using contact holes and connection plugs, then signal transfer is enabled, but diffusion area increases and misalignment occurs
Solution Approach 1:
The patent moves the interconnection from the surface plane to the subsurface dimension by forming conductive lines within the STI region below the original semiconductor surface. This dimensional transition eliminates the need for surface contact holes and reduces diffusion area requirements while maintaining reliable signal transfer through vertical connecting plugs.
Solution Approach 2:
The patent introduces connecting plugs as intermediary structures that vertically bridge the surface contact region and the subsurface conductive lines. These plugs serve as mediators to transfer signals from the transistor contact holes through the STI region to the underground interconnection lines, enabling reliable connection without requiring large surface diffusion areas.
2Manufacturing precision
If larger diffusion areas are designed to accommodate photolithographic misalignment, then contact holes remain within transistor regions, but capacitance increases and AC performance deteriorates
Solution Approach 1:
By relocating the interconnection to the subsurface STI region, the patent creates a self-aligned structure where the connecting plugs naturally define the contact region boundaries. This eliminates the need for oversized diffusion areas to compensate for lithographic misalignment, thereby reducing parasitic capacitance and improving AC performance while maintaining manufacturing tolerance.
3Reliability
If conventional metal wire interconnections are used, then transistors are connected for signal transfer, but chip area increases and power consumption rises
Solution Approach 1:
The patent utilizes the vertical dimension by forming conductive lines within the STI region below the semiconductor surface. This subsurface interconnection approach significantly reduces the surface footprint required for power and signal distribution, enabling higher transistor density and reduced chip area while maintaining reliable transistor connections.
Solution Approach 2:
The STI region, traditionally serving only as electrical isolation, is repurposed to host conductive interconnection lines. This multi-functional use of the STI region simultaneously provides isolation and interconnection, eliminating the need for separate surface metal layers and reducing overall chip area while maintaining reliable transistor connections.
4Power
If surface metal layers are used for power delivery, then transistors receive power, but resistance and power consumption increase
Solution Approach 1:
The patent forms power delivery conductors within the subsurface STI region, creating shorter and more direct current paths compared to surface metal layers. This dimensional relocation reduces the resistive path length and cross-sectional area, thereby lowering resistance and power consumption while effectively delivering power to transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces resistance and parasitic capacitance, minimizes chip size, and lowers power consumption by providing a more efficient method for signal and power transmission, allowing for further scaling and performance enhancement of integrated circuits.
Implementation Method 1
a first underground interconnection line within the first STI region and positioned under the original semiconductor surface, wherein the first underground interconnection line extends along the first direction, and the first conductive region of each PMOS transistor is electrically connected to the first underground interconnection line
Data Source
AI summary
The present invention discloses a semiconductor circuit structure with underground interconnection lines within the semiconductor substrate for signal and power delivery. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a first set of PMOS transistors formed based on the semiconductor substrate, and each PMOS transistor comprising a gate structure, a first conductive region, and a second conductive region; a first shallow trench isolation (STI) region neighboring to the first set of PMOS transistors and extending along a first direction; a first underground interconnection line within the first STI region and positioned under the original semiconductor surface, wherein the first underground interconnection line extends along the first direction, and the first conductive region of each PMOS transistor is electrically connected to the first underground interconnection line; and a first power voltage electrically connected to the first underground interconnection line through a first connecting via.