Semiconductor Underlayer Etching to Prevent Array Region Shorts
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Solution Overview
Problem
The challenge of electrical shorts within the array region of semiconductor devices due to shrinking isolation structure spacing in memory cells, such as DRAM, adversely affects device performance.
Innovation Solution
A method involving the formation of a patterned mask structure, etching stop layer, and underlayer, with defect distribution mapping and process condition adjustment to reduce defects and prevent electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If isolation structure spacing is shrunk to increase memory cell density, then productivity and storage capacity are improved, but electrical shorts occur in the array region reducing reliability
Solution Approach 1:
The patent divides the array region into multiple sections by forming separation structures between adjacent memory cell arrays. These separation structures physically segment the continuous array region, preventing electrical shorts between adjacent cells while maintaining high density. The segmentation is achieved through selective removal of sacrificial layers and formation of isolation structures at specific locations.
Solution Approach 2:
The patent introduces sacrificial layers as intermediary structures during the fabrication process. These sacrificial layers are formed between adjacent memory cell arrays and are subsequently removed to create separation structures. The intermediary sacrificial layers enable precise control over the spacing and formation of final isolation structures, ensuring proper electrical isolation while maintaining manufacturing feasibility.
2Ease of manufacture
If conventional etching process is used without underlayer, then manufacturing process is simpler, but defects occur in array region affecting device performance
Solution Approach 1:
The patent applies preliminary actions by forming an underlayer structure before performing the etching process. This underlayer is deposited over the sacrificial layers and patterned mask, providing a protective and supportive foundation during etching. The preliminary formation of this underlayer prevents defects such as etching breakthroughs and maintains dimensional accuracy, thereby improving manufacturing precision without significantly complicating the overall process.
Solution Approach 2:
The underlayer acts as a cushioning layer that protects the underlying structures during the etching process. By providing this protective barrier beforehand, the patent prevents direct exposure of sensitive layers to aggressive etchants, reducing the risk of defects and ensuring more controlled etching. This cushioning effect maintains manufacturing precision while keeping the process relatively simple.
Data Source
AI summary
A method of manufacturing the same is provided. The method includes providing a substrate. The method also includes forming a target layer over the substrate. The method further includes forming a patterned mask structure over the target layer. In addition, the method includes forming an etching stop layer over the patterned mask structure. The method also includes forming an underlayer over the etching stop layer; and performing an etching process to pattern the target layer.