Underlying Metal Layer Recess for Semiconductor Bonding
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Solution Overview
Problem
The existing methods for forming bump electrodes in semiconductor devices face challenges with side etching during wet etching, which reduces the bonding strength between the barrier metal layer and the underlying metal layer, leading to lower yield and reliability, especially as chip size and integration density increase.
Innovation Solution
The formation of a recess or projection under the barrier metal layer, with the underlying metal layer following the shape of these features, increases the bonding area and prevents side etching, ensuring a strong and reliable electric connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wet etching is used to remove the underlying metal layer, then the unnecessary metal can be removed efficiently, but side etching occurs which reduces the bonding area and weakens the bonding strength
Solution Approach 1:
The patent applies preliminary action by forming a protective film on the underlying metal layer before etching. This protective film prevents side etching from occurring in the first place, thereby preserving the bonding area and maintaining bonding strength while still allowing efficient removal of unnecessary metal through the etching process.
2Productivity
If the chip size is increased to accommodate higher integration density, then more components can be integrated, but the bonding area becomes smaller relative to the chip size, reducing bonding strength
Solution Approach 1:
The patent applies local quality by selectively forming a protective film only in regions where side etching would occur, rather than uniformly across the entire chip. This localized approach preserves the bonding area in critical regions while maintaining the benefits of high integration density on the chip.
3Productivity
If the bonding area is reduced to accommodate smaller bump electrodes, then higher density connections can be achieved, but the bonding strength decreases
Solution Approach 1:
The patent applies beforehand cushioning by forming a protective film that acts as a buffer against side etching. This protective layer compensates for the reduced bonding area by preventing further loss of bonding material during etching, thereby maintaining bonding strength even with smaller bump electrodes and higher connection density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the bonding strength between the external connection electrode and the substrate, improving the reliability and yield of the electronic component by maintaining a larger bonding area despite side etching, thus supporting high-density and high-performance semiconductor devices.
Implementation Method 1
an underlying metal layer 22 is formed on the pad electrode 14 and the passivation layer 20
Implementation Method 2
a barrier metal layer 26 is formed by electrolytic plating on the underlying metal layer 22
Data Source
AI summary
Herein disclosed an electronic component having a passivation layer in which an opening that exposes a part of a pad electrode is formed, an underlying metal layer formed on the pad electrode and the passivation layer, and a barrier metal layer formed on the underlying metal layer for an external connection electrode, the electronic component including a recess or/and a projection configured to be provided under the barrier metal layer outside or/and inside the opening, the underlying metal layer being formed on the recess or/and the projection and having a surface shape that follows the recess or/and the projection.