Un-doped Capping Layer for HEMT Uniformity and Breakdown Voltage
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Solution Overview
Problem
Existing high electron mobility transistors (HEMTs) face challenges in device uniformity and hysteresis, which affect their performance in ultra-high voltage applications, particularly in terms of stability and reliability.
Innovation Solution
Incorporating an un-doped silicon-containing capping layer between the gate structure and the doped compound semiconductor layer to protect it from high temperature and energy processes, thereby improving device uniformity and reducing hysteresis, and enhancing breakdown voltage and saturation current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p-type III-V semiconductor is used as a band adjustment layer to achieve higher threshold voltage for ultra-high voltage applications, then the breakdown voltage and electron mobility are improved, but device uniformity and hysteresis performance deteriorate
Solution Approach 1:
An un-doped capping layer is introduced as an intermediary between the doped compound semiconductor layer and the gate structure. This capping layer acts as a mediator that protects the doped layer from high temperature and high energy processes during gate formation, thereby maintaining device uniformity while still achieving the desired high breakdown voltage through the underlying doped structure
Solution Approach 2:
The un-doped capping layer is formed in advance before the high temperature and high energy processes of gate structure fabrication. This preliminary protective action prevents damage to the doped compound semiconductor layer before it can occur, ensuring device uniformity is maintained throughout subsequent manufacturing steps
2Reliability
If a p-type III-V semiconductor is used as a band adjustment layer to achieve higher threshold voltage, then the breakdown voltage is improved, but hysteresis effect increases
Solution Approach 1:
The un-doped capping layer serves as a protective intermediary that isolates the doped compound semiconductor layer from the high temperature and high energy processes during gate structure formation. This prevents the generation of hysteresis-causing defects in the doped layer while maintaining the electrical performance needed for high breakdown voltage
Solution Approach 2:
The capping layer provides beforehand cushioning protection to the doped compound semiconductor layer against thermal and energetic damage during subsequent processing. This pre-protective measure prevents the formation of harmful states that would cause hysteresis, while allowing the doped structure to maintain its high breakdown voltage characteristics
3Ease of manufacture
If high temperature and high energy processes are applied during gate structure formation, then the gate structure is properly formed, but the doped compound semiconductor layer is damaged
Solution Approach 1:
The un-doped capping layer acts as a thermal and energetic barrier between the gate structure formation processes and the doped compound semiconductor layer. This intermediary layer allows standard high temperature and high energy gate formation processes to proceed while protecting the underlying doped layer from damage
Solution Approach 2:
The capping layer functions as a thin film protective shell that covers and shields the doped compound semiconductor layer during subsequent processing. This thin film barrier allows manufacturing processes to proceed without compromising the quality of the protected layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly improves device uniformity by 2 to 5 folds, reduces hysteresis by 10 folds, and increases saturation current, while also increasing breakdown voltage by forming an NP junction that reduces gate leakage.
Implementation Method 1
Incorporating an un-doped silicon-containing capping layer between the gate structure and the doped compound semiconductor layer to protect it from high temperature and energy processes
Implementation Method 2
protect it from high temperature and energy processes
Implementation Method 3
increasing breakdown voltage by forming an NP junction that reduces gate leakage
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a substrate; a buffer layer on the substrate; a channel layer on the buffer layer; a barrier layer on the channel layer; a doped compound semiconductor layer on a portion of the barrier layer; an un-doped first capping layer on the doped compound semiconductor layer; a gate structure on the un-doped first capping layer; and source/drain structures on opposite sides of the gate structure. There is a channel region in the channel layer that is adjacent to the interface between the channel layer and the barrier layer.