Undulating Via Interconnect Structure for Lower Resistance Contacts
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Solution Overview
Problem
The scaling down of integrated circuits (ICs) to smaller technology nodes poses challenges in spacing between gate structures and source/drain features, contacts, and metallization lines, leading to increased resistance and complexity in interconnect structures.
Innovation Solution
The implementation of non-linear, undulating-shaped vias in interconnect structures that increase the contact area and reduce the path length between transistor terminals and metal lines, thereby reducing contact and sheet resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional linear vias are used in scaled-down ICs, then manufacturing process is simpler, but contact resistance and sheet resistance increase
Solution Approach 1:
The patent applies curvature by replacing conventional linear via structures with undulating-shaped vias that follow a curved, wave-like path through the dielectric layer. This curved geometry increases the contact area between the via and adjacent conductive features (source/drain regions and metal lines), thereby reducing contact resistance and sheet resistance while maintaining manufacturing feasibility through standard photolithography and etching processes.
2Productivity
If spacing between gate structures and source/drain features is reduced for scaling, then device density increases, but resistance of interconnect structures increases
Solution Approach 1:
The patent addresses the resistance issue in scaled-down devices by transitioning from a two-dimensional planar contact interface to a three-dimensional undulating contact interface. The undulating via structure creates multiple contact points along its curved path, effectively increasing the contact area without increasing the planar footprint, thus reducing resistance while maintaining high device density.
3Reliability
If conventional linear vias are used, then via path length is shorter, but contact area is reduced leading to higher resistance
Solution Approach 1:
The patent changes the geometric parameters of the via structure by introducing an undulating profile with controlled amplitude and wavelength. This parameter change increases the effective contact area between the via and adjacent conductive features, reducing contact resistance. The via path length increases modestly due to the curved path, but this is acceptable given the significant reduction in resistance achieved through the increased contact area.
Data Source
AI summary
A method and device according to the present disclosure includes a substrate that has a first transistor terminal such as a source feature and a second transistor terminal such as another source feature. Contact structures are formed on each source/drain feature. After forming the contact structures, a via opening is formed in dielectric materials above the contact structures, which is filled to form a non-linear via that extends from the contact on the first source feature to the contact on the second source feature. The non-linear via may include an outline in a top view of an undulating-shape having convex and/or concave portions.