Uneven Die Stacking for Tapered Wire Bond Clearance
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in increasing semiconductor die count within a given footprint and thickness, particularly in wire bonding due to tight proximity and physical interference, which hinders the development of high-density, compact semiconductor packages.
Innovation Solution
A semiconductor package design with staggered and differently thicknessed semiconductor dies, creating a tapered wire bond zone that enhances wire bonding clearance by using progressively staggered stacks with varying die thicknesses and offsets, allowing for increased die counts while maintaining dimensional constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor dies are stacked in tight proximity to increase die count, then the die count within a given footprint is improved, but wire bonding becomes difficult due to physical interference
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional staggered stack configuration. Dies are arranged in multiple layers with horizontal offsets, creating a tapered profile that extends vertically and diagonally. This dimensional change provides wire bonding clearance in the vertical and diagonal spaces, allowing wires to be routed without interfering with adjacent dies while maintaining high die density within the footprint.
Solution Approach 2:
The patent implements nested stacking where multiple dies are arranged in concentric or overlapping patterns. Inner dies are positioned within the footprint defined by outer dies, with each die layer staggered relative to the previous layer. This nesting approach maximizes the utilization of the available footprint area while maintaining physical clearance for wire bonding operations through the tapered configuration.
2Ease of operation
If semiconductor dies are stacked with varying thicknesses to create tapered wire bond zone, then wire bonding clearance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by using dies with different thicknesses at specific positions within the stack. Outer dies have greater thickness than inner dies, creating a tapered profile where the thickness varies locally rather than uniformly throughout. This localized variation in die thickness provides the necessary clearance for wire bonding in critical areas while maintaining a relatively simple overall stack structure that is manageable with standard manufacturing processes.
Data Source
AI summary
Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a first stack of first semiconductor dies on a substrate, wherein the first stack has a first stepped profile that extends above the substrate and toward a central axis of the substrate; a second stack of second semiconductor dies on the substrate, wherein the second stack has a second stepped profile that extends above the substrate and toward the central axis of the substrate; and a tapered wire bond zone between the first stack and the second stack, wherein a width of the tapered wire bond zone away from a surface of the substrate is greater than a width of the tapered wire bond zone proximate the surface of the substrate.