Uneven Heat Spreader Structure for Low-ESD Semiconductor Packaging

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Solution Overview

Problem

Semiconductor packages accumulate electric charges during manufacturing, leading to electrical stress and potential damage when these charges are discharged.

Innovation Solution

The semiconductor package incorporates a heat dissipation member with a surface featuring a plurality of uneven structures, which reduces the accumulation of electric charges by increasing the distance between the package and external metals, thereby decreasing capacitance and electrical stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional semiconductor package with a flat surface is used, then the manufacturing process is simple, but electric charges accumulate leading to electrical stress and potential damage

Engineering Contradiction:
Improvereduction of electrical stress and damageVSAvoidstructure of heat dissipation member
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies dimensionality change by transitioning from a flat two-dimensional surface to a three-dimensional uneven surface with protruding structures. This dimensional transformation increases the distance between the heat dissipation member and external metals, thereby reducing capacitance and electrical stress while maintaining manufacturing feasibility through molding processes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The heat dissipation member's surface is segmented into multiple protruding uneven structures rather than a continuous flat surface. This segmentation creates multiple isolated regions that collectively reduce the overall capacitance area, effectively lowering charge accumulation and electrical stress during manufacturing.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the distance between the semiconductor package and external metals is increased to reduce capacitance, then electrical stress is reduced, but the package size increases

Engineering Contradiction:
Improvereduction of capacitance and electrical stressVSAvoidpackage dimensions
Core Design Contradiction:
ReliabilityVSVolume of moving object

Solution Approach 1:

Instead of increasing the horizontal distance between the package and external metals, the patent utilizes the vertical dimension by creating protruding structures that extend upward. This approach reduces capacitance through increased vertical separation while maintaining a compact horizontal footprint, thus avoiding significant increases in overall package volume.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If uneven structures are added to the heat dissipation member, then charge accumulation is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improvereduction of electric charge accumulationVSAvoidmanufacturing process of heat dissipation member
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges the formation of uneven structures with the existing molding process of the heat dissipation member. By integrating the creation of protruding structures into the standard molding operation, the patent avoids adding separate manufacturing steps, thereby maintaining ease of manufacture while achieving the desired charge reduction effect.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively reduces the amount of electric charges accumulated in the semiconductor package, minimizing electrical stress and potential damage during the manufacturing process, while also reducing development costs and time.

Implementation Method 1

a magnitude of capacitance formed between the heat dissipation member and metal objects is influenced by the plurality of uneven structures

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS12347795B2Semiconductor package including uneven structures and electronic device including the same
Publication Date: 2025.07.01 SAMSUNG ELECTRONICS CO LTD
  • US12347795B2 patent drawing
  • US12347795B2 patent drawing
  • US12347795B2 patent drawing

AI summary

A semiconductor package includes a package board, at least one semiconductor chip disposed on the package board, a molding member disposed on the package board and at least partially surrounding the at least one semiconductor chip, and a heat dissipation member disposed on the at least one semiconductor chip and the molding member. The molding member has first region in which a plurality of uneven structures are disposed, and a second region spaced apart from an external region by the plurality of uneven structures. The plurality of uneven structures protrude to a predetermined height away from the semiconductor chip, the molding member, and the heat dissipation member, and may be formed as a part of the head dissipation member, or formed separately.