Unidirectional Data Mapping for Flash Memory Write Latency
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Solution Overview
Problem
Flash memory's write asymmetry leads to increased write latency, affecting overall system performance in computing devices, as it requires writing large groups of cells to change data values, complicating data management and prolonging write times.
Innovation Solution
A data mapping technique that reduces average write latency by writing data values in one direction without simultaneously writing in the opposite direction, utilizing a controller with mapping circuitry to select storage states that minimize reset operations, thereby reducing overall write time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If flash memory writes data in both directions (0 to 1 and 1 to 0), then data can be updated independently in each cell, but write latency increases due to the need to write large groups of cells (erase blocks) simultaneously
Solution Approach 1:
The patent applies asymmetry by mapping data values to storage element states such that only transitions in one direction (e.g., from state representing '1' to state representing '0') are performed, avoiding the need for bidirectional writes. This asymmetric mapping resolves the contradiction by eliminating the time-consuming group write operations while preserving independent cell update capability through selective unidirectional transitions.
Solution Approach 2:
The patent changes the parameter of state transition direction by mapping logical data values to physical storage states in a controlled manner. By defining that only certain state transitions (e.g., high resistance to low resistance) are permitted during normal writes, the system achieves fast independent cell updates without requiring the slow group erase operations that would be needed for bidirectional writes.
2Reliability
If flash memory implements complex logic to preserve valid data during erase block operations, then data integrity is maintained, but device complexity increases
Solution Approach 1:
The asymmetric mapping approach simplifies the management logic by eliminating the need for complex tracking of valid data locations within erase blocks. Since writes occur in one direction only and do not require group operations, the system inherently preserves data integrity without needing sophisticated logic to identify and protect valid data during write operations.
Solution Approach 2:
The patent extracts the complex data management logic from the memory control system by using a simpler mapping scheme that naturally preserves data integrity. The asymmetric state transitions remove the need for complex erase block management, valid data tracking, and coordination logic, thereby reducing device complexity while maintaining reliability.
3Speed
If new non-volatile memory technologies (RRAM, MRAM) enable bidirectional writes without group operations, then write speed improves, but write asymmetry optimization opportunities are lost
Solution Approach 1:
The patent applies asymmetry to RRAM and MRAM technologies by intentionally mapping data values to storage element states such that only unidirectional transitions are used, even though bidirectional writes are physically possible. This optimization leverages the inherent speed advantage of these technologies while reducing write operations to a single direction, thereby maintaining both high speed and mapping optimization flexibility.
Solution Approach 2:
The patent changes the operational parameter from bidirectional to unidirectional state transitions in RRAM and MRAM devices. By mapping logical values to physical states in a controlled manner that permits only one transition direction, the system achieves optimized write performance that leverages the fast write capability of these technologies while reducing unnecessary bidirectional operations.
Data Source
AI summary
A data storage device includes a memory and a controller. Mapping circuitry is configured to apply a mapping to received data to generate mapped data to be stored in storage elements. The mapping is configured to reduce average write time by mapping at least one incoming data value into a mapped value such that no transitions of storage elements from a second state to a first state are used for storing the mapped value into the storage elements. The mapping of the received data to the mapped data does not depend on the states of the storage elements prior to the writing of the mapped data.