Unidirectional Memory Metal Layout for SADP Compatibility
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Solution Overview
Problem
Current integrated circuit designs face challenges in achieving compatibility between memory cells and standard functional cells due to the incompatibility of unidirectional metal structures, particularly at 10 nm or smaller node sizes, leading to inefficiencies and errors in circuit design and fabrication.
Innovation Solution
The implementation of a unidirectional metal layout configuration in memory cells, where metal features in one direction are formed in a first metal layer and another set in a perpendicular direction in a second layer, ensuring compatibility with standard cells by using Self-Aligned-Double-Patterning (SADP) techniques, allowing for the formation of bit lines and routing lines that match standard cell configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If unidirectional metal layout is used in memory cells to improve compatibility with SADP processes, then manufacturing precision and scalability are improved, but device complexity increases due to the need for separate unidirectional routing in multiple metal layers
Solution Approach 1:
The metal interconnect system is segmented into different functional layers: first metal layer handles vertical unidirectional routing for memory cell compatibility, while second metal layer handles horizontal unidirectional routing for standard cell compatibility. This segmentation allows each layer to be optimized independently for its specific routing direction and function.
Solution Approach 2:
The solution transitions from planar bidirectional routing to three-dimensional unidirectional routing by utilizing multiple metal layers with distinct orientation constraints. Vertical unidirectional lines in the first metal layer combine with horizontal unidirectional lines in the second metal layer to achieve complete connectivity while maintaining SADP process compatibility.
2Ease of manufacture
If bidirectional metal routing is used to simplify layout design, then ease of manufacture is improved, but compatibility with SADP processes and standard cell integration deteriorates
Solution Approach 1:
Different metal layers are assigned different routing quality constraints: the first metal layer implements strict vertical unidirectional routing to ensure SADP compatibility in memory cell regions, while the second metal layer implements horizontal unidirectional routing for standard cell regions. This local quality differentiation ensures SADP compatibility is maintained where required without unnecessarily constraining overall design flexibility.
3Adaptability or versatility
If metal features are formed in multiple directions within the same layer, then routing flexibility is improved, but manufacturing precision and pattern formation accuracy deteriorate due to SADP process constraints
Solution Approach 1:
The routing function is segmented across multiple metal layers, with each layer dedicated to a specific routing direction. This segmentation enables each layer to maintain manufacturing precision for unidirectional patterns while collectively providing the flexibility of multi-directional routing through vertical and horizontal components in different layers.
Solution Approach 2:
The solution resolves the conflict between routing flexibility and manufacturing precision by adding the layer dimension to the routing architecture. Instead of attempting to form multi-directional patterns in a single layer, the system uses vertically-oriented patterns in the first layer and horizontally-oriented patterns in the second layer, achieving equivalent routing flexibility through three-dimensional layout while maintaining SADP-compatible unidirectional patterning in each layer.
Data Source
AI summary
At least one method, apparatus and system disclosed involves an integrated circuit comprising a unidirectional metal layout. A first set of metal features are formed in a vertical configuration in a first metal layer of a memory cell. A second set of metal features are formed in a unidirectional horizontal configuration in a second metal layer of the memory cell. A third set of metal features are formed in the unidirectional horizontal configuration in a second metal layer of a functional cell for providing routing compatibility between the memory cell and the functional cell. The memory cell is placed adjacent to the functional cell for forming an integrated circuit device.