Unidirectional Semiconductor Wiring for Integration Density
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing integration density and improving electrical characteristics while maintaining low power consumption and high performance, particularly in the design of logic cells and memory devices.
Innovation Solution
The semiconductor device incorporates a unidirectional structure for first wires, allows for easy disposition changes of contact plugs with fine pitch, and features a common conductive line with a non-shared structure to enhance electrical characteristics, including the use of contact plugs and via plugs at specific vertical levels to connect logic cells efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional multi-directional wire structures are used, then routing flexibility is maintained, but integration density decreases
Solution Approach 1:
The wire structure is segmented into unidirectional first wires and second wires arranged in alternating directions at different vertical levels, allowing each segment to be optimized independently for density while maintaining overall routing capability
Solution Approach 2:
The patent transitions from planar multi-directional wiring to a three-dimensional structure with wires at multiple vertical levels, using the vertical dimension to resolve routing conflicts that would otherwise require complex horizontal wire crossings, thereby increasing integration density
2Manufacturing precision
If contact plugs are positioned at standard locations, then fabrication is straightforward, but fine pitch and custom disposition are difficult to achieve
Solution Approach 1:
The contact plug positions are made dynamically adjustable through selective formation at different vertical levels and locations, allowing optimization for fine pitch applications while maintaining standard fabrication processes for conventional designs
Solution Approach 2:
Contact plugs are formed at specific vertical levels before wire deposition, allowing precise positioning and pitch control to be established early in the fabrication process, which simplifies subsequent manufacturing steps
3Reliability
If shared conductive lines are used, then device complexity is reduced, but electrical characteristics deteriorate
Solution Approach 1:
The conductive line network is segmented into dedicated first wires and second wires that serve specific logic cells independently, eliminating shared conductive lines and their associated electrical interference, with each segment optimized for its specific function
Solution Approach 2:
Different wire structures are assigned to different regions and functions within the semiconductor device, with first wires and second wires having distinct configurations optimized for their specific electrical requirements, improving overall electrical characteristics
Data Source
AI summary
Provided is a semiconductor device including a substrate with a plurality of logic cells, transistors provided in the plurality of logic cells, contact plugs connected to electrodes of the transistors, first via plugs in contact with top surfaces of the contact plugs, and first wires in contact with top surfaces of the first via plugs. The first wires may include a common conductive line connected to the plurality of logic cells through the contact plugs, and all of the first wires may be shaped like a straight line extending parallel to a specific direction.