Unified Address Mapping Table for Mixed Memory Storage
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Solution Overview
Problem
Existing storage devices face inefficiencies in mapping addresses across different types of memories, leading to increased overhead and latency in data access operations.
Innovation Solution
A method of registering address mapping information for different types of memories in a single address mapping table, using flag bits and address ranges to determine storage areas, allowing for synthetic mapping and improved performance in data read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate address mapping tables are used for different types of memories, then address mapping can be performed for each memory type, but overhead and latency in data access operations increase
Solution Approach 1:
The patent combines multiple separate address mapping tables for different memory types into a single unified address mapping table. This table stores mapping information for both volatile and nonvolatile memories together, using a unified logical address space that maps to physical addresses across different memory types. This merging eliminates the need for separate mapping operations and reduces overhead, directly improving data access speed while maintaining the ability to handle different memory types.
Solution Approach 2:
The unified address mapping table serves multiple functions simultaneously: it maps logical addresses to physical addresses in volatile memory, maps logical addresses to physical addresses in nonvolatile memory, and provides a single interface for both read and write operations across different memory types. This multi-functionality reduces the complexity of managing separate mapping tables while maintaining comprehensive address mapping capabilities.
2Loss of time
If a unified address mapping table is used for different types of memories, then overhead and latency are reduced, but determining the correct storage area requires additional flag bit checks
Solution Approach 1:
The patent extracts the memory type identification information into separate flag bits within the physical address structure. Each physical address includes specific flag bits that indicate whether the address corresponds to volatile or nonvolatile memory. This extraction allows the system to quickly determine the correct storage area through simple bit checks rather than complex queries, reducing access latency while maintaining clear storage area identification.
Solution Approach 2:
The patent applies different address structures with specific flag bits for different storage areas within the unified mapping table. Volatile memory addresses include volatile memory-specific flag bits, while nonvolatile memory addresses include nonvolatile memory-specific flag bits. This local differentiation within the unified structure enables efficient identification of storage areas without requiring separate mapping tables, balancing reduced latency with accurate storage area detection.
Data Source
AI summary
In a method of mapping an address in a storage device, first address mapping information including a first physical address and a first logical address is registered in an address mapping table. The first physical address corresponds to a first storage area in the storage device. The first storage area includes a first type of memory. The first logical address corresponds to the first physical address. Second address mapping information including a second physical address and a second logical address is registered in the address mapping table. The second physical address corresponds to a second storage area in the storage device. The second storage area includes a second type of memory that is different from the first type of memory. The second logical address corresponds to the second physical address.