Unified Address Refresh Circuit for DRAM Power Reduction

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Solution Overview

Problem

Existing DRAM technologies face challenges in efficiently refreshing normal and redundancy addresses within the same refresh cycle, leading to increased power consumption and chip area due to separate refresh commands and decoding processes.

Innovation Solution

An address refresh circuit and method that includes a selection circuit and a decoding circuit. The selection circuit acquires strobe, redundancy, and normal address signals and selects one as a target address signal within specific pulse durations based on the strobe signal. The decoding circuit decodes the target address signal to output a decoded signal, allowing both normal and redundancy addresses to be refreshed within the same refresh cycle.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate refresh commands and decoding processes are used for normal and redundancy addresses, then reliability of data retention is improved, but power consumption increases

Engineering Contradiction:

Improvedata retentionVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent merges the refresh operations for normal addresses and redundancy addresses into a single unified refresh command. The selection circuit multiplexes between normal address signals and redundancy address signals based on a refresh mode signal, allowing both types of addresses to be refreshed within the same refresh cycle through one decoding process, thereby reducing power consumption while maintaining data retention reliability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The refresh circuit is designed with multi-functionality to handle both normal address refresh and redundancy address refresh operations. The selection circuit and decoding circuit can universally process either normal addresses or redundancy addresses by switching based on the refresh mode signal, eliminating the need for separate dedicated circuits for each refresh type.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If separate refresh commands and decoding processes are used for normal and redundancy addresses, then reliability of data retention is improved, but chip area increases

Engineering Contradiction:

Improvedata retentionVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines the refresh functionality for normal and redundancy addresses into a single integrated circuit block. By merging the address selection and decoding functions into one unified structure with a selection circuit that multiplexes between different address sources, the chip area required for refresh operations is significantly reduced compared to having separate independent refresh circuits.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The unified refresh circuit possesses universal functionality to perform both normal address refresh and redundancy address refresh operations. The selection circuit and decoding circuit can adaptively handle different address types based on the refresh mode signal, eliminating the need for duplicate circuitry and thereby reducing overall chip area.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If separate refresh commands are used for normal and redundancy addresses, then reliability of data retention is improved, but bandwidth resources are wasted

Engineering Contradiction:

Improvedata retentionVSAvoidbandwidth resources

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent merges multiple refresh commands into a single unified refresh command that can service both normal addresses and redundancy addresses. The selection circuit responds to one refresh command by switching between normal address mode and redundancy address mode, thereby reducing the number of commands transmitted and consuming less bandwidth resource while ensuring both address types are refreshed.

Inventive Principle:

Principle #5Merging (Combining)

4Use of energy by moving object

If unified processing is used for normal and redundancy addresses, then power consumption is reduced, but device complexity increases

Engineering Contradiction:

Improvepower consumptionVSAvoidcircuit complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The unified refresh circuit is segmented into distinct functional modules: a selection circuit for multiplexing between normal and redundancy addresses, and a decoding circuit for processing the selected addresses. This segmentation allows the circuit to maintain reduced power consumption through unified processing while managing complexity through modular design, where each module has a specific function.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS12308065B2Address refresh circuit and method, memory, and electronic device

Publication Date: 2025.05.20 CHANGXIN MEMORY TECH INC

AI summary

An address refresh circuit and method, a memory, and an electronic device are provided. The address refresh circuit includes a selection circuit and a decoding circuit. The selection circuit is configured to acquire a strobe signal, a redundancy address signal and a normal address signal, and select, within each of a first pulse duration and a second pulse duration and based on the strobe signal, one of the redundancy address signal or the normal address signal as a target address signal; the first pulse duration and the second pulse duration belong to the same refresh cycle, and the second pulse duration is later than the first pulse duration. The decoding circuit is configured to decode the target address signal to obtain and output a decoded signal.