Unified Address Space for Host-Slave Memory Sharing
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Solution Overview
Problem
In existing computing systems with multiple discrete computing devices, the collaborative data access efficiency of device memories is low, necessitating an improved method for sharing device memories across different computing devices.
Innovation Solution
A computing system and method that utilize a host computing device and a slave computing device connected through a data bus, where both devices maintain memory page tables for mapping virtual addresses to physical addresses, allowing for unified system physical address space access, enabling efficient data sharing and access management between devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device memories of discrete computing devices are used independently without sharing mechanisms, then each device has dedicated memory access capability, but collaborative data access efficiency between devices is low
Solution Approach 1:
The patent merges the address spaces of host device and slave device into a unified system physical address space. The host device memory and slave device memory are combined under a single address space management system, allowing seamless access across device boundaries without complex inter-device communication protocols.
Solution Approach 2:
The system implements a universal address mapping mechanism that serves multiple functions: it enables memory sharing between devices, provides virtual-to-physical address translation, and supports both host and slave device access patterns through a single unified interface.
2Speed
If a unified system physical address space is implemented across multiple devices, then data access efficiency improves, but address mapping management complexity increases
Solution Approach 1:
The address mapping management is segmented into device-specific components. Each device (host and slave) maintains its own memory page table and address mapping management unit, dividing the complex global address translation task into manageable local segments that can be independently maintained and updated.
Solution Approach 2:
The system introduces a unified system physical address space as an intermediary layer between virtual addresses and physical memory locations. This intermediary abstraction simplifies the mapping process by providing a standard translation mechanism that handles device-specific address spaces transparently.
3Ease of operation
If device memories are shared through a unified address space, then programming simplicity improves, but memory access control difficulty increases
Solution Approach 1:
The unified system physical address space provides a universal access interface that works consistently across all devices. Programming code can access memory using the same address space conventions regardless of which device the memory resides on, eliminating the need for device-specific access logic while maintaining secure control through the underlying mapping mechanisms.
Data Source
AI summary
A computing system includes a host computing device and a slave computing device. The host computing device comprises a host processor, a host device memory and a host address mapping management. The host address mapping management manages a system memory page table, and converts, in response to a data access request from a processing process run on the host processor, requested virtual addresses into host device physical addresses based on the system memory page table to allow the processing process to access corresponding host storage units. The slave computing device includes a slave processor callable by the host processor to assist the host processor in running the processing processes, a slave device memory and a slave address mapping management unit. The slave address mapping unit converts, in response to a data access request of the processing process, requested virtual addresses into slave device physical addresses based on the slave device memory page table, to allow the slave processor to access corresponding slave storage units to assist the host processor in running the processing process.