Unified Address Space for Multiple Interconnect Links
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Solution Overview
Problem
Modern data centers face challenges in providing a unified address space for multiple links, leading to increased software complexity and difficulty in managing bandwidth across different interconnects, as existing solutions either complicate virtualization or require managing multiple address domains independently.
Innovation Solution
The implementation of an address translation and security check unit (ATU) or address translation cache (ATC) on the accelerator device, which maps guest-physical addresses to host-physical addresses, allowing multiple physical links to be treated as a single logical link, reducing software complexity and enabling dynamic bandwidth management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple physical links are managed with separate address domains, then link-specific address translation can be performed, but software complexity increases and management becomes difficult
Solution Approach 1:
The patent merges multiple physical links into a single logical link, allowing the CPU to interact with all links through one unified address domain. The address translation unit (ATU) on the device performs address translation for all links, eliminating the need for separate address domains while maintaining address translation accuracy. This reduces software complexity by presenting a single device interface to the CPU.
Solution Approach 2:
The address translation unit (ATU) acts as an intermediary between the CPU and multiple physical links. It receives address translation requests from the CPU, translates addresses according to link-specific mappings, and returns translated addresses. This intermediary handles the complexity of multiple address domains internally while presenting a simple unified interface to the CPU.
2Reliability
If separate address domains are used for each link, then address translation can be performed, but bandwidth management across links becomes difficult
Solution Approach 1:
By combining multiple physical links into one logical link with a unified address domain, the system enables centralized bandwidth management. The ATU maintains address translation tables for all links and can dynamically allocate bandwidth across links based on workload requirements, simplifying bandwidth management while preserving address translation capability.
Solution Approach 2:
The system dynamically manages bandwidth allocation across multiple links through the ATU, which can adjust address translation mappings in real-time based on bandwidth requirements. This dynamic capability allows flexible bandwidth management while maintaining accurate address translation for all links.
3Device complexity
If a unified address space is provided for multiple links, then software complexity is reduced, but address translation for link-specific addresses becomes challenging
Solution Approach 1:
The ATU serves as an intermediary that handles address translation within the device. It receives addresses from the CPU in the unified address domain, translates them to link-specific addresses using maintained translation tables, and routes them to the appropriate physical link. This preserves address translation accuracy while maintaining software simplicity.
Solution Approach 2:
The device performs address translation autonomously through its integrated ATU, without requiring complex software intervention. The ATU maintains translation tables and automatically translates addresses based on link-specific mappings, enabling the device to self-manage address translation while the CPU sees a simple unified interface.
Data Source
AI summary
There is disclosed in one example an apparatus, including: a plurality of interconnects to communicatively couple an accelerator device to a host device; and an address translation module (ATM) to provide address mapping between host-physical address (HPA) and guest-physical address (GPA) spaces for the accelerator device, wherein the plurality of devices share a common GPA domain and wherein address mapping is to be associated with only one of the plurality of interconnects.