Unified Address Translation Cache for Dynamic Workload Adaptation
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Solution Overview
Problem
Existing address translation cache systems inefficiently utilize resources by separating storage for full and partial translation data, leading to suboptimal performance under varying workload conditions.
Innovation Solution
A unified address translation cache that allows any entry to store either full or partial translation data, with control circuitry dynamically allocating and identifying the type of data stored, enabling flexible and efficient use of resources based on workload demands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If address translation cache resources are hard partitioned between TLB and walk cache, then resource allocation is simplified and management is easier, but resource utilization efficiency deteriorates under varying workload conditions
Solution Approach 1:
The patent implements a unified address translation cache that can store both full address translations (TLB function) and partial address translations (walk cache function) in the same physical storage structure. The cache entries are designed to accommodate different types of address translation data through type identification fields, allowing the same hardware resources to serve multiple address translation purposes dynamically based on workload requirements
2Ease of operation
If separate structures are provided for TLB and walk cache, then functional separation is achieved and management is simplified, but circuit resource consumption increases
Solution Approach 1:
The patent merges the previously separate TLB and walk cache structures into a single unified address translation cache. This consolidation eliminates redundant hardware resources while maintaining the functional capabilities of both full and partial address translation storage. The unified structure uses shared physical storage with logical separation through entry type identification, reducing overall circuit resource consumption
3Productivity
If a unified cache stores multiple types of address translation data, then resource utilization efficiency improves, but the complexity of allocation and management increases
Solution Approach 1:
The patent applies local quality by associating type identification data with each individual cache entry. This allows the allocation process to quickly determine the type of data stored in each entry based on local entry characteristics rather than requiring global cache state analysis. The type identification is embedded at the entry level, enabling efficient differentiation and allocation decisions for full versus partial address translations
Data Source
AI summary
An apparatus and method are provided for maintaining address translation data within an address translation cache. The address translation cache has a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. The address translation cache is used to store address translation data of a plurality of different types representing address translation data specified at respective different levels of address translation within a multiple-level page table walk. The plurality of different types comprises a final level type of address translation data that identifies a full translation from the virtual address to the physical address, and at least one intermediate level type of address translation data that identifies a partial translation of the virtual address. The control circuitry is arranged, when performing the allocation process, to apply an allocation policy that permits each of the entries to be used for any of the different types of address translation data, and to store type identification data in association with each entry to enable the type of the address translation data stored therein to be determined. Such an approach enables very efficient usage of the address translation cache resources, for example by allowing the proportion of the entries used for full address translation data and the proportion of the entries used for partial address translation data to be dynamically adapted to changing workload conditions.