Unified Baseband Architecture with Shared Memory Scheduler
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Solution Overview
Problem
Conventional baseband systems in communication networks are inflexible and require significant redesign to support different radio protocols and standards, making them inefficient for processing various transmission formats and protocols, especially with the rapid evolution of radio standards and demand for new features.
Innovation Solution
A unified baseband architecture that incorporates a CPU subsystem with integrated DSPs, hardware functional elements, and general-purpose CPUs, along with a shared memory and scheduler, enabling programmable pipeline processing to support multiple radio protocols across various mobile technology generations, including 3G, 4G, and beyond.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional baseband systems use fixed pipelined stages implemented with multiple devices (FPGA, ASIC, DSP), then specific protocol processing is achieved, but adaptability to different radio protocols and standards deteriorates
Solution Approach 1:
The patent implements a universal baseband processing architecture where a single reconfigurable platform can handle multiple radio protocols (3G, 4G, LTE, and future standards) through programmable functional elements. The system uses a unified device structure with configurable processing stages that can be programmed via PCIe interface to support different protocols without requiring separate dedicated hardware for each standard.
Solution Approach 2:
The baseband processing system employs dynamic reconfigurability where the pipelined stages can be modified at runtime through software programming. The functional elements can be dynamically allocated and reconfigured to process different protocol types, allowing the system to adapt to evolving radio standards without physical hardware changes.
2Adaptability or versatility
If baseband systems are redesigned to support different protocols, then protocol versatility improves, but device complexity and redesign effort increase
Solution Approach 1:
The patent creates a universal baseband processor that consolidates multiple protocol-specific processing functions into a single reconfigurable device. This eliminates the need for separate dedicated hardware for each protocol, reducing overall system complexity while maintaining versatility through software-based configuration.
Solution Approach 2:
The system changes operational parameters through software programming rather than hardware redesign. The functional elements can be reconfigured by modifying processing parameters, data flow configurations, and algorithm implementations, allowing protocol adaptation without structural hardware changes.
3Productivity
If multiple devices are used for pipelined stages, then processing functionality is achieved, but system integration complexity increases
Solution Approach 1:
The patent merges multiple discrete baseband processing devices into a single integrated platform. The unified architecture combines what would traditionally require separate FPGA, ASIC, and DSP devices into one cohesive system accessible through a single PCIe interface, simplifying integration while maintaining processing capabilities.
Solution Approach 2:
The integrated device is internally segmented into functional processing stages that can be independently configured and programmed. This segmentation allows complex processing tasks to be divided into manageable functional elements within the unified device, maintaining productivity while reducing integration complexity.
Data Source
AI summary
Methods and apparatus for a unified baseband architecture. In an exemplary embodiment, an apparatus includes a shared memory having a plurality of access ports and a scheduler that outputs scheduled jobs. Each scheduled job identifies data processing to be performed. The apparatus also includes a plurality of functional elements coupled to the plurality of access ports, respectively, to access the shared memory. Each functional element is operable to retrieve selected data from the shared memory, process the selected data to generate processed data, and store the processed data into the shared memory based on a received scheduled job.