Unified BIST Control via Test Control Bus for Semiconductor Testing
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Solution Overview
Problem
The existing test methods for semiconductor devices with multiple BIST circuits require complex control operations and redundant resources, as each BIST circuit has independent control commands and expected value comparisons, leading to increased test time and reduced port availability for normal operations, and do not support the linkage of BISTs with normal tests.
Innovation Solution
A test apparatus with a control unit that generates signals to integrate and synchronize multiple BIST circuits via a test control bus, allowing for unified control and result acquisition, enabling simultaneous execution of BIST and normal tests without the need for additional external access ports.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple BIST circuits are controlled independently with separate control commands, then each BIST circuit can be tested individually, but the control operation becomes complex and test time increases
Solution Approach 1:
The patent merges control of multiple independent BIST circuits into a unified control structure. A single control signal from the test apparatus simultaneously activates multiple BIST circuits, consolidating what would otherwise require separate control sequences. This reduces control operation complexity while maintaining the ability to test each function block individually, as the interface circuit within the DUT manages the distributed BIST circuits under unified command.
2Reliability
If multiple BIST circuits are tested with independent control commands, then comprehensive testing is achieved, but test time increases due to redundant operations
Solution Approach 1:
The patent enables continuous parallel testing of multiple BIST circuits through unified control. Instead of sequentially executing independent test sequences for each BIST circuit, the system activates all relevant BIST circuits simultaneously under a single control signal, allowing continuous useful action across multiple function blocks. This parallel execution maintains test completeness while significantly reducing total test time.
3Adaptability or versatility
If JTAG ports are assigned to DC test and input leak test, then multiple test types can be performed, but port availability for normal operations is reduced
Solution Approach 1:
The patent segments the testing function by implementing BIST circuits directly within the DUT's function blocks. This internal segmentation allows each function block to perform its own self-test independently, eliminating the need to share external JTAG ports between normal operation and testing. The segmentation of testing control to the functional block level preserves full port availability for normal operations while enabling comprehensive multi-type testing through the unified control interface.
Data Source
AI summary
An interface circuit is connected to an ATE via a test control bus BUS3 that differs from main buses, receives a control signal output from the ATE, and controls multiple BIST circuits according to the control signal. Furthermore, a DUT is configured such that a test result signal specified by the control signal can be read by the ATE via the test control bus. A BISI synchronous control unit generates a first control signal for individually controlling the multiple BIST circuits included in the DUT, and a second control signal for reading the test result signal generated by the BIST circuit, and supplies these signals to the DUT via the test control bus.