Unified Block Vector Resolution Signaling for Video Decoding
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Solution Overview
Problem
Existing video coding technologies face challenges in efficiently encoding and decoding video data, particularly in reducing redundancy and managing bitrates effectively, especially for high-resolution videos.
Innovation Solution
The proposed solution involves a method and apparatus for video encoding/decoding that utilizes intra block copy mode to determine a block vector, allowing for efficient reconstruction of samples within a current block based on a unified resolution syntax for both intra block copy and inter picture merge modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separate resolution syntax is used for intra block copy mode and inter picture merge mode, then each mode can be optimized independently, but the device complexity and coding overhead increase
Solution Approach 1:
The patent merges the resolution syntax for intra block copy mode and inter picture merge mode into a unified structure. The same resolution syntax elements are used for both modes, eliminating the need for separate resolution signaling and reducing overall syntax complexity while maintaining independent optimization capability through mode-specific interpretation of the unified syntax.
Solution Approach 2:
The resolution syntax is designed to serve multiple functions across different prediction modes. A single set of resolution syntax elements is universally applicable to both intra block copy mode and inter picture merge mode, allowing the same syntax structure to handle resolution information for different block vector types without requiring mode-specific duplication.
2Ease of manufacture
If separate resolution syntax is used for intra block copy mode and inter picture merge mode, then each mode can have mode-specific optimization, but the bitrate increases due to redundant signaling
Solution Approach 1:
The patent combines resolution signaling for both modes into a single unified syntax structure. Instead of transmitting separate resolution information for intra block copy and inter picture merge modes, the encoder transmits a unified resolution syntax that both modes share, thereby reducing redundant signaling and lowering bitrate while preserving mode-specific optimization capabilities.
3Device complexity
If unified resolution syntax is used for intra block copy mode and inter picture merge mode, then the device complexity and bitrate are reduced, but the flexibility for mode-specific optimization decreases
Solution Approach 1:
The patent applies local quality by allowing different interpretation and usage of the unified resolution syntax within each mode. While the syntax structure is unified, each mode (intra block copy and inter picture merge) can apply mode-specific processing and optimization strategies to the resolution information, maintaining adaptability through localized customization rather than requiring separate syntax structures.
4Measurement precision
If high resolution is used for block vectors in intra block copy mode, then the sample reconstruction accuracy improves, but the bitrate increases
Solution Approach 1:
The patent implements dynamic resolution adaptation where the resolution of block vectors in intra block copy mode is not fixed but can be adjusted based on content characteristics and bitrate constraints. The unified resolution syntax enables flexible resolution selection that adapts to different coding scenarios, allowing high resolution when accuracy is critical and lower resolution when bitrate is constrained, thereby optimizing the trade-off between reconstruction accuracy and bitrate.
Data Source
AI summary
Aspects of the disclosure provide methods and apparatuses for video decoding. In some examples, an apparatus includes processing circuitry. The processing circuitry decodes prediction information of a current block from a coded video bitstream. Based on an intra block copy mode being applied to the current block, the processing circuitry infers a vector resolution flag indicates that a resolution of a block vector is integer-pel, determines the resolution of the block vector based on resolution information that is included in the prediction information, determines the block vector according to the determined resolution, and reconstructs at least one sample of the current block according the block vector.


