Unified Buffer for SONET/SDH Latency Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Implementing a SONET/SDH add/drop multiplexer node with low latency is challenging due to delays from ingress FIFO, ingress timeslot interchange, time-division multiplexed fabric, egress timeslot interchange, and egress FIFO, which are difficult to manage within the stringent latency budget of 25 microseconds for high-order tributaries and 50 microseconds for low-order tributaries.
Innovation Solution
A hybrid data and circuit stream management system using a unified fabric that optimizes latency by removing the ingress FIFO, combining circuit-to-packet and packet-to-circuit converter functions, and sharing storage elements to reduce the data path latency, while meeting the conventional SONET/SDH ADM node latency requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional SONET/SDH add/drop multiplexer node architecture is used with separate ingress FIFO, timeslot interchange, and egress FIFO components, then the system can handle circuit and packet traffic, but the latency exceeds the stringent requirements of 25 microseconds for high-order tributaries and 50 microseconds for low-order tributaries
Solution Approach 1:
The patent merges the ingress FIFO, timeslot interchange, and egress FIFO into a single unified buffer structure. This consolidation eliminates the multiple separate components that contributed to latency, while the unified buffer still provides the necessary functionality for both circuit and packet traffic handling. The merging reduces the number of data copy operations and synchronization points, directly addressing the latency issue while maintaining manageable complexity.
Solution Approach 2:
The unified buffer structure serves multiple functions simultaneously: it acts as both an ingress buffer and egress buffer, performs timeslot interchange operations, and handles both circuit and packet traffic types. This multi-functionality eliminates the need for separate dedicated components for each function, reducing overall node complexity while achieving the required latency performance through streamlined data paths.
2Productivity
If multiple separate components (ingress FIFO, timeslot interchange, egress FIFO) are used in the SONET/SDH node, then the system can perform complex circuit and packet switching operations, but the data path latency increases beyond acceptable limits
Solution Approach 1:
The patent combines multiple switching operations into a unified buffer structure that performs ingress buffering, timeslot interchange, and egress buffering in a single integrated component. This merging eliminates the sequential processing delays that occurred when data passed through multiple separate components, thereby reducing latency while maintaining the efficiency of complex switching operations through the unified structure's optimized data paths.
3Loss of time
If the latency budget of 25 microseconds for high-order tributaries and 50 microseconds for low-order tributaries is strictly enforced, then latency requirements are met, but traditional node architectures with multiple processing stages cannot achieve this performance
Solution Approach 1:
The patent segments the unified buffer structure into distinct operational regions for ingress processing and egress processing, allowing independent optimization of each function while maintaining tight integration. This segmentation enables the system to meet stringent latency requirements by ensuring that each segment operates efficiently within the overall latency budget, while the modular segmented design maintains implementation feasibility through structured organization.
Solution Approach 2:
The patent merges the ingress and egress buffering functions into a single unified buffer structure, eliminating the latency overhead of separate buffer management and data copying operations. This merging achieves the required latency compliance by reducing the total processing time, while the unified structure simplifies implementation compared to coordinating multiple separate buffers, thereby improving ease of manufacture.
Data Source
AI summary
Techniques for transmitting SONET/SDH traffic over an Advanced Switching compatible switch fabric. In one implementation, SONET/SDH traffic may be aggregated and encapsulated into Advanced Switching compatible packets. In one implementation, the contents of the Advanced Switching compatible packets may be configurable and directions on how to unpack the Advanced Switching compatible packets may be transmitted to end point nodes. In one implementation, SONET/SDH pointer justification generation may be divided between a source node which transmits SONET/SDH traffic to the switch fabric and an end point node which receives SONET/SDH traffic from the switch fabric.