Unified Cache Coherency Management via Domain Segmentation
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Solution Overview
Problem
In processing devices with multiple processor cores, the congestion of interconnects due to snoop operations in unified caches is exacerbated as more cores are utilized, leading to inefficiencies in maintaining coherency and increased bandwidth usage.
Innovation Solution
Implementing a coherency management system where cachelines are marked as coherent or incoherent, allowing for non-global snoops in response to incoherent read accesses, reducing the need for global queries and thereby minimizing interconnect congestion and bandwidth usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all information in unified cache is kept coherent, then cache coherency is maintained, but interconnect congestion increases due to global snoop operations
Solution Approach 1:
The patent segments the coherency management by introducing separate coherency domains for instruction caches and data caches. Instruction cache accesses operate in an incoherent domain where global snoops are not required, while data cache accesses operate in a coherent domain where global snoops are performed. This segmentation allows the system to maintain coherency only where necessary (data) while avoiding unnecessary global snoops for instructions, thereby reducing interconnect congestion.
Solution Approach 2:
The patent applies local quality by treating instruction and data caches differently within the same unified cache structure. Instruction cache lines are marked with a domain bit indicating they belong to the incoherent domain, while data cache lines belong to the coherent domain. This allows different coherency management strategies to be applied locally to different types of data within the same cache, optimizing both coherency maintenance and interconnect utilization.
2Reliability
If global snoop operations are performed for every cache miss, then coherency is maintained across all cores, but interconnect congestion compounds with more processor cores
Solution Approach 1:
The patent divides the coherency management into two separate domains: an incoherent domain for instruction caches and a coherent domain for data caches. By segmenting the snoop operations accordingly, global snoops are performed only for data cache misses where coherency is required, while instruction cache misses bypass the global snoop mechanism. This segmentation prevents interconnect traffic from compounding with additional cores for instruction accesses.
Solution Approach 2:
The patent extracts the coherency requirement from instruction cache operations by placing them in an incoherent domain. Instruction cache misses no longer trigger global snoop operations, effectively removing the source of unnecessary interconnect traffic. Only data cache misses, which truly require coherency maintenance, continue to generate global snoop operations.
3Productivity
If unified caches store both instruction and data information, then cache utilization is improved, but coherency management complexity increases
Solution Approach 1:
The patent applies local quality by assigning different coherency domain characteristics to different types of cache lines within the unified cache. Each cache line includes a domain bit that identifies whether it belongs to the instruction cache (incoherent domain) or data cache (coherent domain). This allows the unified cache to maintain high utilization while managing coherency complexity locally by treating different cache lines differently based on their domain assignment.
Solution Approach 2:
The patent segments the unified cache into two functional domains: an incoherent domain for instruction storage and a coherent domain for data storage. This segmentation is implemented through domain bits in cache line tags and separate snoop filter entries for each domain. The segmentation allows the system to benefit from unified cache utilization while managing coherency complexity by applying different rules to different domains.
Data Source
AI summary
Each cacheline of a unified cache storing information is marked as incoherent if the information was acquired incoherently or marked as coherent if the information was acquired coherently. A subsequent incoherent read access to a cacheline can result in a cache hit and a return of the cached information regardless of whether the cacheline is marked as coherent or incoherent. However, a subsequent coherent read access to a cacheline marked as incoherent will be returned as a cache miss regardless of whether the cacheline includes information sought by the coherent read access. In response to a cache miss for a coherent read access, a global snoop is initiated so as to query all other target components within the same coherency domain. In contrast, a cache miss resulting from an incoherent read access is processed using a non-global snoop to a limited set of one or a few target components in the coherency domain.