Unified Cache for Coherent and Non-Coherent Data
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current data processing systems face inefficiencies in managing both coherent and non-coherent data, with coherent caches limited in size and latency-sensitive locations, and non-coherent caches requiring additional software management for coherency, leading to suboptimal resource utilization and increased latency.
Innovation Solution
A single cache system that dynamically allocates cache lines as either shareable or non-shareable, enabling the storage of both coherent and non-coherent data, functioning as an eviction cache for the coherent domain and reducing off-chip memory traffic by migrating dirty shareable cache lines without writing to memory, thus optimizing resource allocation and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate coherent and non-coherent caches are used, then data coherency management is simplified for each domain, but resource utilization is suboptimal and latency increases
Solution Approach 1:
The patent merges separate coherent and non-coherent caches into a single unified cache structure. The cache controller dynamically manages cache lines, allocating them as shareable or non-shareable based on domain requirements. This consolidation improves resource utilization by allowing both domains to share the same physical cache resources while maintaining proper coherency management through domain-specific access protocols and cache line state tracking.
Solution Approach 2:
The unified cache serves multiple functions simultaneously - it acts as a coherent cache for the first domain and a non-coherent cache for the second domain. The cache controller implements multi-functional management by detecting the source domain of access requests and applying appropriate coherency protocols, thereby making a single cache structure universally applicable to both coherent and non-coherent domains.
2Speed
If coherent cache is located in latency-sensitive location, then access speed is improved, but cache size is limited
Solution Approach 1:
By merging coherent and non-coherent cache functions into a single unified structure, the system achieves both high-speed access (inherent in coherent cache design) and large cache capacity (characteristic of non-coherent caches). The unified cache is positioned to serve both domains, with the controller dynamically allocating cache lines based on access patterns and domain requirements, thereby achieving both speed and size benefits simultaneously.
3Quantity of substance
If non-coherent cache is located closer to memory controllers, then cache size can be larger, but latency increases
Solution Approach 1:
The unified cache located near memory controllers serves dual purposes - providing large capacity for non-coherent domain storage while also functioning as an eviction cache for the coherent domain. The cache controller intelligently manages cache line allocation, allowing the same physical structure to fulfill both roles, thereby achieving large capacity without the latency penalty typically associated with non-coherent cache locations.
4Productivity
If dynamic allocation of cache lines is implemented, then resource allocation is optimized, but cache management complexity increases
Solution Approach 1:
The cache implementation uses dynamic allocation where cache lines can be transitioned between shareable and non-shareable states based on runtime requirements. The cache controller monitors access patterns and domain requirements, dynamically adjusting cache line allocation and state. This dynamic approach optimizes resource utilization while the controller manages complexity through automated state tracking and domain-aware allocation policies.
Data Source
AI summary
The present disclosure advantageously provides a system cache and a method for storing coherent data and non-coherent data in a system cache. A transaction is received from a source in a system, the transaction including at least a memory address, the source having a location in a coherent domain or a non-coherent domain of the system, the coherent domain including shareable data and the non-coherent domain including non-shareable data. Whether the memory address is stored in a cache line is determined, and, when the memory address is not determined to be stored in a cache line, a cache line is allocated to the transaction including setting a state bit of the allocated cache line based on the source location to indicate whether shareable or non-shareable data is stored in the allocated cache line, and the transaction is processed.