Unified Cache Way Partitioning for Adaptive Error Detection
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Solution Overview
Problem
Unified caches in data processing systems face challenges in balancing error detection reliability with performance, as existing error detection codes (EDC/ECC) increase complexity and reduce performance, failing to meet the varying needs of users who prioritize either safety or efficiency.
Innovation Solution
Implementing a way-partitioning scheme in unified caches, where each way is allocated for specific information types (instruction, data, or both) and configured to use either multi-bit EDC or single-bit parity checking, allowing dynamic selection of error detection schemes based on allocation control registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If EDC/ECC error detection schemes are used in unified caches, then error detection capability is improved, but device complexity and performance are worsened
Solution Approach 1:
The unified cache is segmented into multiple ways, and different error detection schemes can be applied to different ways. The allocation control register divides the cache into instruction storage ways and data storage ways, allowing selective application of EDC/ECC to instruction ways while using simpler parity for data ways, thus resolving the contradiction between error detection capability and device complexity
Solution Approach 2:
Different error detection schemes are applied locally to different parts of the cache based on their specific requirements. Instruction storage ways that require high reliability use EDC/ECC, while data storage ways use simpler parity checking, allowing each part to have the appropriate level of error detection without unnecessarily increasing overall complexity
2Reliability
If EDC/ECC error detection schemes are used in unified caches, then error detection capability is improved, but performance is reduced
Solution Approach 1:
By segmenting the cache into different ways with different error detection requirements, the performance penalty of EDC/ECC is limited to only those ways that need high reliability (instruction ways), while data ways maintain high performance through simpler parity checking, thus resolving the contradiction between error detection capability and performance
Solution Approach 2:
The error detection parameter is changed dynamically based on the allocation mode. When a way is allocated for instruction storage, EDC/ECC is enabled; when allocated for data storage, simpler parity is used. This parameter change allows the system to optimize between reliability and performance based on actual usage requirements
3Adaptability or versatility
If way-partitioning with dynamic error detection selection is implemented, then adaptability is improved, but device complexity is increased
Solution Approach 1:
The allocation control register serves multiple functions: it controls way allocation (instruction vs. data storage) and simultaneously controls the selection of error detection schemes. This multi-functionality allows the system to adapt to different requirements without adding separate control mechanisms, thus improving adaptability while minimizing the increase in device complexity
Data Source
AI summary
In a data processing system processing circuitry executes a plurality of data processing instructions. A unified cache memory stores data and instructions processed by the processing circuitry. The unified cache memory has a plurality of sets, each set having a plurality of ways, each with one or more information fields. Cache memory control circuitry has a control register for controlling allocation of each way of the plurality of ways for one of: (1) a first type of information; (2) a second type of information; or (3) both the first type of information and the second type of information. The cache memory control circuitry further individually controls a selection of a type of error detection among a plurality of types of error detection for each way of the unified cache memory based upon the allocation control indicated by the control register.