Unified Cache Management Circuit Using Hit Rate Thresholds
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Solution Overview
Problem
In virtualization environments, conventional cache management circuits using the LRU algorithm face challenges in managing unified caches, leading to premature eviction of metadata, increased CPU read/write cycles, latency, and network congestion due to the insertion of data entries that displace metadata entries, resulting in inefficient data retrieval across networks.
Innovation Solution
An improved unified cache management circuit that analyzes the cache hit rate ratio (CHRR) to prevent or allow data receipt based on pre-determined thresholds, incrementing an alert counter when the CHRR is low, preventing data receipt until the CHRR improves, thereby reducing CPU cycles and network congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the LRU algorithm is used to manage unified cache, then cache management is simple, but metadata entries are prematurely evicted and cache hit rate decreases
Solution Approach 1:
The patent changes the cache management parameter from simple LRU eviction to a threshold-based admission control mechanism. By monitoring the cache hit rate ratio (CHRR) and comparing it against predefined thresholds, the system dynamically adjusts data entry admission decisions, thereby improving cache hit rate while maintaining manageable complexity through parameter-driven control.
Solution Approach 2:
The patent implements a feedback mechanism where the cache hit rate ratio is continuously monitored and fed back to the cache management circuit. This feedback loop enables the system to adapt its behavior by preventing data entry admissions when CHRR is below the upper threshold, thus protecting metadata integrity and maintaining high cache hit rates.
2Quantity of substance
If data entries are allowed to displace metadata entries in unified cache, then cache utilization increases, but latency increases and network congestion occurs
Solution Approach 1:
The patent applies preliminary anti-action by proactively preventing data entry admissions when the cache hit rate ratio falls below the upper threshold. This preventive measure stops the harmful displacement of metadata entries before it can occur, thereby avoiding the subsequent latency increases and network congestion that would result from metadata evictions and repeated cache misses.
3Reliability
If alert counter is incremented frequently due to low CHRR, then cache protection is improved, but CPU read/write cycles increase
Solution Approach 1:
The patent applies partial action by implementing a threshold-based alert mechanism that only triggers protective measures when the cache hit rate ratio falls below the upper threshold. This selective approach provides adequate metadata protection while avoiding excessive CPU intervention, as the system only actively manages cache admissions when necessary rather than continuously.
Data Source
AI summary
An exemplary embodiment herein is a method including comparing a cache hit rate ratio of a unified cache to a first pre-determined threshold, incrementing an alert counter in response to the cache hit rate ratio being lower than the first pre-determined threshold, comparing the alert counter to a pre-determined limit, preventing a first receipt of a type of data by the unified cache in response to the alert counter being equal to the pre-determined limit, causing a second receipt of metadata by the unified cache, comparing the cache hit rate ratio to a second pre-determined threshold, and allowing the first receipt of the type of data by the unified cache in response to the cache hit rate ratio being greater than the second pre-determined threshold.