Unified Cache Partitioning for Instruction Data Contention
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Solution Overview
Problem
Current processor-based systems with unified caches face inefficiencies in accessing instructions and data due to the lack of specific partitioning within the cache hierarchy, leading to increased latency and contention between instruction and data access.
Innovation Solution
The system partitions the unified cache into distinct portions for storing only instructions and only data, with an allocation controller dynamically managing these partitions based on usage patterns to optimize cache allocation and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a unified cache is used to store both instructions and data, then cache capacity is maximized and space utilization is improved, but access latency increases and contention between instruction and data access occurs
Solution Approach 1:
The unified cache is segmented into a first portion dedicated to storing instructions and a second portion dedicated to storing data. This segmentation allows the cache to maintain high capacity while reducing access latency by directing instruction accesses to the first portion and data accesses to the second portion, thereby eliminating contention between instruction and data access operations.
2Device complexity
If a unified cache is used without partitioning, then device complexity is reduced and ease of operation is improved, but access speed deteriorates due to contention
Solution Approach 1:
The cache structure is segmented into distinct first and second portions for instructions and data respectively. This segmentation improves access speed by preventing contention between instruction and data access, while maintaining relatively simple operation through dedicated access paths to each portion.
3Loss of time
If separate L1 caches for instructions and data are used, then access latency is reduced by placing caches near respective entities, but device complexity increases and cache capacity is reduced
Solution Approach 1:
Separate L1 instruction cache and L1 data cache structures are merged into a single unified cache with distinct first and second portions. This merging maintains the low access latency benefits of separate caches by providing dedicated storage regions, while reducing device complexity by consolidating the cache hierarchy into one structure.
Data Source
AI summary
The present invention provides a method and apparatus for allocating space in a unified cache. The method may include partitioning the unified cache into a first portion of lines that only store copies of instructions retrieved from a memory and a second portion of lines that only store copies of data retrieved from the memory.