Unified Cache Memory Management for Portable Devices
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Solution Overview
Problem
Consumer electronic devices face memory management challenges due to increasing algorithm complexity, leading to high memory usage, latency, and power consumption, especially in portable devices where traditional memory management units result in frequent disk access and high power consumption.
Innovation Solution
A computational system with a memory management unit that uses a common virtual memory space to access and store task instructions and data, moving them between non-volatile storage and cache memory efficiently, reducing the need for frequent disk access and minimizing power consumption by avoiding writes to non-volatile storage when switching tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional memory management units are used to manage task-specific virtual addressing, then instructions and data can be moved to physical memory locations, but frequent disk access occurs resulting in large power consumption
Solution Approach 1:
The patent merges instruction sets and data into a single unified cache memory space, eliminating the need for separate instruction and data memory management. This consolidation reduces the frequency of disk accesses by allowing both instructions and data to be loaded together into the same cache, thereby reducing power consumption while maintaining automated memory management capabilities.
Solution Approach 2:
The cache memory is designed to serve multiple functions: storing both instruction sets and data, and acting as a unified buffer between the processor and non-volatile storage. This multi-functional approach reduces the need for specialized memory management operations that would otherwise require frequent disk accesses, thus lowering power consumption while preserving ease of operation.
2Loss of time
If small intermediate level caches (level 2 or level 3) are used to store frequently used instruction sets, then memory access latency is reduced, but product cost increases due to expensive SRAM
Solution Approach 1:
The patent implements a nested memory hierarchy where the unified cache memory is positioned between the processor and non-volatile storage, creating a nested structure that provides fast access to frequently used instructions and data without requiring expensive SRAM. The cache is strategically placed to intercept and satisfy memory requests, reducing latency while maintaining cost-effectiveness through the nested architecture.
Solution Approach 2:
The unified cache memory acts as an intermediary between the processor and non-volatile storage, buffering frequently accessed instructions and data to reduce memory access latency. This intermediary structure avoids the need for expensive SRAM by using a more cost-effective cache implementation that still provides the latency reduction benefits needed for real-time processing.
3Adaptability or versatility
If manual overlays are used to manage memory by programmatically moving code, then memory can be allocated, but programmer effort increases and memory management becomes difficult for large programs
Solution Approach 1:
The unified cache memory system provides self-service memory management by automatically loading required instruction sets and data into the cache based on processor access patterns. This eliminates the need for programmers to manually manage memory allocation and code movement, reducing programmer effort while maintaining the adaptability needed for large programs and multiple tasks through automated decision-making about what to cache.
Data Source
AI summary
The disclosure is directed to a computational system including a processor, cache memory accessible to the processor, and a memory management unit accessible to the processor. The processor is configured to access a virtual memory space to perform a first task and is configured to access the virtual memory space to perform a second task. The virtual memory space references first and second sets of task instructions associated with the first and second tasks, respectively. The virtual memory space references non-instruction data associated with the first task. The cache memory is configured to store the first set of task instructions and the non-instruction data. The memory management unit is configured to determine the physical memory location of the second set of task instructions. The computational system is configured to not write the first set of task instructions and the non-instruction data to a physical location beyond the cache memory.