Unified Cache Structure for Translation Table Entry Access
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Solution Overview
Problem
The existing systems face inefficiencies in managing translation table entries (TTEs) due to small page sizes and large physical memory sizes, leading to a high number of TTEs that cannot be cached, resulting in overhead and complex hardware and software handling.
Innovation Solution
A unified cache structure that simultaneously stores program instructions, program data, and TTEs, allowing for efficient access and management of TTEs by using a processor with a unified cache that balances access patterns and eliminates the need for a dedicated memory management unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a unified cache structure is used to store both program data and TTEs, then cache space utilization is improved, but the complexity of cache management increases
Solution Approach 1:
The patent combines the data cache and TTE cache into a single unified cache structure. The cache controller manages both program data and translation table entries within the same physical cache memory, eliminating the need for separate cache structures. This merging approach improves space utilization by allowing the cache to dynamically allocate space between data and TTEs based on current workload requirements.
Solution Approach 2:
The unified cache structure serves multiple functions: it stores both program data and translation table entries, and can adapt its behavior based on the type of access requested. The cache controller determines whether an access is for data or TTEs and routes it appropriately within the same cache structure, making the cache multi-functional rather than dedicated to a single purpose.
2Loss of time
If TTEs are cached in the unified cache, then access time is improved, but the number of cache lines required increases
Solution Approach 1:
The unified cache dynamically adjusts the allocation of cache lines between data and TTEs based on current system needs. Rather than having a fixed partition, the cache controller can shift cache lines between storing program data and storing translation table entries depending on the workload. This dynamic behavior allows the system to optimize for TTE access time when needed while efficiently using available cache lines.
3Measurement precision
If specialized translation hardware is used to handle TTEs, then translation accuracy is improved, but hardware complexity increases
Solution Approach 1:
The cache controller is designed to handle both data cache operations and TTE cache operations through a single unified structure. Rather than having separate specialized hardware paths for data and translation, the same cache controller manages both types of accesses, determining the appropriate operation based on the request type. This reduces hardware complexity while maintaining translation accuracy through proper control logic.
Data Source
AI summary
One embodiment provides a system that includes a processor with a unified cache structure that facilitates accessing translation table entries (TTEs). This unified cache structure can simultaneously store program instructions, program data, and TTEs. During a memory access, the system receives a virtual memory address. The system then uses this virtual memory address to identify one or more cache lines in the unified cache structure which are associated with the virtual memory address. Next, the system compares a tag portion of the virtual memory address with the tags for the identified cache line(s) to identify a cache line that matches the virtual memory address. The system then loads a translation table entry that corresponds to the virtual memory address from the identified cache line.