Unified Chip Architecture via Segmented Via Fabrication
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Solution Overview
Problem
Current semiconductor technologies face challenges in creating precise, repeatable, and cost-effective electrical connections through electronic chips, particularly with deep vias, high-frequency signal transmission, and the need for controlled capacitance and resistance, while avoiding damage to active semiconductor devices and accommodating diverse chip designs and materials.
Innovation Solution
A process involving front-end and back-end wafer processing to create interconnected metal traces, allowing for the bonding of wafers to form unified chips with through-wafer electrical connections that can carry opposite charges and support high-speed signals, using narrow vias and precise control of capacitance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional via processes are used to create through-chip electrical connections, then electrical connectivity is achieved, but manufacturing precision deteriorates due to difficulty in creating precise, repeatable connections through deep vias
Solution Approach 1:
The patent segments the via fabrication process into multiple stages: forming vias through the first substrate, bonding substrates together, and then completing via formation through the bonded structure. This segmentation allows each stage to be optimized independently, improving overall manufacturing precision while easing fabrication complexity.
Solution Approach 2:
The patent performs preliminary actions by forming via holes and applying conductive materials to the first substrate before bonding occurs. This preliminary via formation allows for better control and precision in the via creation process, as the via structure is established while the substrate is still accessible and can be precisely patterned.
2Ease of manufacture
If large via widths are used to improve via fabrication ease, then manufacturing precision deteriorates due to loss of signal integrity and increased capacitance
Solution Approach 1:
The patent transitions from planar via structures to three-dimensional via structures that extend through bonded substrates. By utilizing the vertical dimension created through substrate bonding, the invention achieves precise via placement and controlled dimensions that maintain signal integrity while being manufacturable through advanced bonding techniques.
3Reliability
If deep vias are used to achieve through-chip connections, then electrical connectivity is improved, but manufacturing precision deteriorates due to difficulty in maintaining via alignment and charge control
Solution Approach 1:
The patent segments the deep via structure into multiple shallower via portions formed in separate substrates that are then bonded together. Each via portion is easier to align and control independently, and the bonding process joins these segments to form the complete through-chip electrical connection, thereby maintaining alignment precision while achieving deep connectivity.
Solution Approach 2:
The patent uses the bonded substrate interface as an intermediary that facilitates via alignment and charge control. The bonding process creates precise mechanical and electrical interfaces that allow for controlled via formation across the substrate boundary, enabling deep connections while maintaining manufacturing precision through the mediating effect of the bonded structure.
4Ease of operation
If conventional packaging is used for chip-to-chip connections, then assembly is simplified, but device complexity increases due to large pad drivers and non-scaleable packaging
Solution Approach 1:
The patent merges the electrical connection function with the mechanical bonding structure by forming vias that pass through the bonded substrate interface. This integration eliminates the need for separate large pad drivers and complex packaging structures, reducing device complexity while maintaining ease of assembly through direct wafer-to-wafer bonding with embedded electrical connections.
Data Source
AI summary
A method of creating a unified chip involves performing front-end processing on a first wafer, the front end processing creating multiple devices on the wafer, performing back-end processing on a second wafer, the back end processing creating layers of interconnected metal traces arranged to interconnect at least some of the multiple devices to each other, and bonding the first wafer to the second wafer such that the multiple devices on the first wafer are interconnected to each other by the metal traces of the second wafer.