Unified Data Channel Clocking to Reduce Disk Drive Jitter
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Solution Overview
Problem
Existing disk drive systems utilize multiple time base generators for reading, writing, and servo operations, leading to multiple potential sources of jitter due to multiple time domains.
Innovation Solution
A method and apparatus that generate a single time-base frequency signal, which is then modified using various frequency-modification techniques to derive individual clock signals for reading, writing, and servo functions, thereby reducing jitter by unifying the time base.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple time base generators are used for reading, writing, and servo operations, then each function can have its own optimized clock signal, but multiple sources of jitter are introduced due to multiple time domains
Solution Approach 1:
The patent merges multiple separate time base generators into a single unified time base generator that produces a common reference clock signal. This single clock signal is then distributed to all functions (reading, writing, servo operations) through frequency modification circuits, eliminating multiple time domains and their associated jitter sources while maintaining function-specific clock optimization through digital frequency adjustment.
2Reliability
If a single unified time base is used for all functions, then jitter is reduced by eliminating time-domain crossings, but flexibility in controlling individual clock frequencies is limited
Solution Approach 1:
The patent segments the clock distribution system into a unified time base generator that produces a common reference signal, and separate frequency modification circuits for each function. This segmentation allows the single reference clock to be independently adjusted in frequency and phase for each specific function (reading, writing, servo) through digital control, maintaining both jitter reduction and frequency control flexibility.
Solution Approach 2:
The patent implements dynamic frequency and phase adjustment capabilities in the frequency modification circuits, allowing each function's clock signal to be dynamically tuned based on operational requirements. This enables the system to adapt clock frequencies for different functions while all deriving from the same unified time base, combining jitter reduction with operational flexibility.
Data Source
AI summary
A method of clocking a data channel of a storage device includes generating a single time-base frequency signal, deriving from the single time-base frequency signal, using a plurality of frequency-modification techniques, a plurality of individual clock signals, each respective one of the individual clock signals being for clocking a respective one of reading, writing and servo functions of the data channel. When the storage device is a disk storage device having a rotational frequency, generating a single time-base frequency signal may include generating a time-base frequency signal based on the rotational frequency. Deviation of the single time-base frequency from the rotational frequency may be detected, and the deviation may be compensated for. Each technique of the frequency-modification techniques may be a digital frequency-modification technique, such as a digital timing recovery technique or a digital frequency division technique.