Unified Column Control Circuit for DDR SDRAM Read Operations
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Solution Overview
Problem
Current semiconductor devices with DDR SDRAMs face challenges in efficiently performing read and mode register read operations due to the need for sequential command inputs and complex signal generation, which can increase area requirements and operational complexity.
Innovation Solution
The electronic device incorporates a column control circuit and control circuit that generate necessary pulses and signals based on logic levels of chip selection and command addresses, using delay circuits to synchronize and control read and mode register read operations, thereby reducing area and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential command inputs are used for read and mode register read operations, then operational reliability is maintained, but device complexity and area requirements increase
Solution Approach 1:
The patent combines the read operation and mode register read operation into a unified signal generation framework. The column control circuit generates a unified column control pulse that serves both operation types, while the control circuit uses a single read sum signal that is delayed to produce both read control signals and mode register control signals. This merging eliminates the need for separate sequential command handling circuits, reducing device complexity while maintaining operational reliability through consistent signal-based control.
Solution Approach 2:
The control circuit is designed with multi-functionality to handle both read operations and mode register read operations using the same input signals (chip selection signal and command address). The unified column control pulse and read sum signal generation mechanism serves multiple purposes: generating data output control signals, read control signals, and mode register control signals. This universal approach reduces the number of dedicated circuits needed for different operation types, thereby reducing area requirements while maintaining reliable operation.
2Manufacturing precision
If separate signal generation circuits are used for read and mode register read operations, then operational precision is maintained, but area requirements increase
Solution Approach 1:
The patent merges separate signal generation circuits into a unified control architecture. The column control circuit generates a single column control pulse that is processed by the control circuit to produce all necessary control signals for both read and mode register read operations. This consolidation reduces the total circuit area while maintaining operational precision through consistent signal timing and control logic that applies uniformly to both operation types.
Solution Approach 2:
The patent introduces intermediary signals (column control pulse, read sum signal, and delayed read sum signal) that mediate between the input commands and the final control signals. These intermediary signals serve as universal intermediaries for both read and mode register read operations, allowing precise control to be achieved through a compact signal processing path rather than through multiple separate circuits, thereby reducing area while maintaining precision.
3Productivity
If delay circuits are used to synchronize read and mode register read operations, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent uses delay circuits as intermediary elements to synchronize the generation of read control signals and mode register control signals from a single read sum signal. The delay circuit introduces a controlled time offset to the read sum signal to generate a delayed read sum signal, which is then used to generate mode register control signals. This intermediary delay mechanism enables efficient parallel operation handling without requiring complex coordination logic, thus improving productivity while adding minimal circuit complexity.
Solution Approach 2:
The patent changes the timing parameter of the read sum signal by introducing a delay to generate the delayed read sum signal. This parameter change (time delay) allows the control circuit to generate both read control signals and mode register control signals from the same input signal at different time instances, enabling efficient operation synchronization. The delay circuit implements this parameter change with a simple structure, improving productivity without significantly increasing device complexity.
Data Source
AI summary
An electronic device may include: a column control circuit configured to generate a column control pulse and a mode register enable signal, each with a pulse that is generated based on logic levels of a chip selection signal and a command address; and a control circuit configured to generate a read control signal to perform a read operation and a mode register read operation by delaying the column control pulse based on a logic level of the mode register enable signal and configured to generate a mode register control signal to perform the mode register read operation by delaying the column control pulse based on a logic level of the mode register enable signal.