Unified Command Shifter Encoding for Memory Die Area Reduction
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Solution Overview
Problem
Conventional semiconductor memories require multiple redundant command shifters to distinguish between different command types, leading to increased die area and power consumption due to the need for separate circuitry for each command type, especially with longer latencies.
Innovation Solution
Encoding command signals to reduce the number of command shifters by altering pulse widths or using binary encoding, allowing a single command shifter to handle multiple command types, thereby minimizing die area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate command shifters are used for each command type, then command type distinction is ensured, but die area and power consumption increase
Solution Approach 1:
Multiple separate command shifters for different command types are merged into a single shared command shifter. The patent implements a unified command shifter that receives all command types (read, write, refresh, self-refresh) and uses a single encoding scheme to distinguish between them, eliminating the need for duplicate shifter circuits for each command type.
Solution Approach 2:
A universal command shifter is designed to handle multiple command types through a unified encoding approach. The single shifter uses encoded command signals that incorporate command type information, allowing it to universally process reads, writes, refresh, and self-refresh commands without requiring separate dedicated shifters for each function.
2Reliability
If separate command shifters are used for each command type, then command type distinction is ensured, but power consumption increases
Solution Approach 1:
Multiple separate command shifters for different command types are merged into a single shared command shifter. The patent implements a unified command shifter that receives all command types (read, write, refresh, self-refresh) and uses a single encoding scheme to distinguish between them, eliminating the need for duplicate shifter circuits for each command type.
Solution Approach 2:
A universal command shifter is designed to handle multiple command types through a unified encoding approach. The single shifter uses encoded command signals that incorporate command type information, allowing it to universally process reads, writes, refresh, and self-refresh commands without requiring separate dedicated shifters for each function.
3Loss of time
If command shifter size is increased to accommodate longer latencies, then operational latency requirements are met, but die area and power consumption increase
Solution Approach 1:
The command shifter design uses variable latency parameters achieved through selective clock cycle insertion. Instead of increasing the physical size of the shifter to accommodate all possible latencies, the patent dynamically adjusts the number of clock cycles inserted based on the specific command type and required latency, allowing a single shifter of fixed size to handle variable latency requirements.
4Loss of time
If command shifter size is increased to accommodate longer latencies, then operational latency requirements are met, but power consumption increases
Solution Approach 1:
The command shifter design uses variable latency parameters achieved through selective clock cycle insertion. Instead of increasing the physical size of the shifter to accommodate all possible latencies, the patent dynamically adjusts the number of clock cycles inserted based on the specific command type and required latency, allowing a single shifter of fixed size to handle variable latency requirements.
Data Source
AI summary
Apparatuses and methods for reducing a number of command shifters are disclosed. An example apparatus includes an encoder circuit, a latency shifter circuit, and a decoder circuit. The encoder circuit may be configured to encode commands, wherein the commands are encoded based on their command type and the latency shifter circuit, coupled to the encoder circuit, may be configured to provide a latency to the encoded commands. The decoder circuit, coupled to the latency shifter circuit, may be configured to decode the encoded commands and provide decoded commands to perform memory operations associated with the command types of the decoded commands.