Unified Compilation for Logic Verification
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Solution Overview
Problem
In the logic system design verification process, existing methods separately compile hardware description code and software programming code without optimization across connection points, leading to redundant logics and increased run-time data exchange between hardware emulation devices and CPUs, which slows down the verification process.
Innovation Solution
A method and apparatus that use parsers to generate intermediate representations for both hardware and software codes, analyze these representations to identify connection points, and optimize the codes based on exchange information, generating implementable codes that reduce run-time data exchange by breaking down boundaries between hardware and software components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware description code and software programming code are compiled separately without optimization, then the compilation process is simple and independent, but redundant logics are generated and run-time data exchange increases
Solution Approach 1:
The patent merges the compilation processes of hardware description code and software programming code into a unified compilation flow. The unified parser simultaneously parses both code types, and the optimization module jointly optimizes them by analyzing connection points between hardware and software components. This integration eliminates redundant logics and reduces run-time data exchange, directly improving verification speed despite increased compilation complexity.
2Device complexity
If separate compilation is used for hardware and software codes, then compilation independence is maintained, but redundant logics and increased run-time data exchange occur
Solution Approach 1:
The patent applies preliminary action by performing joint optimization of hardware and software codes during the compilation phase. The optimization module analyzes connection points between the two code types and eliminates redundant logics before runtime. This preliminary optimization reduces the amount of data exchange required during verification, thereby reducing verification time without requiring complex runtime modifications.
3Productivity
If joint optimization across connection points is implemented, then run-time performance is improved, but compilation complexity increases
Solution Approach 1:
The patent introduces an intermediary unified parser that handles both hardware description code and software programming code. This intermediary component translates both code types into a common intermediate representation, enabling joint optimization without requiring complex direct integration of separate compilation systems. The unified parser acts as a mediator that simplifies the overall compilation architecture while still enabling cross-language optimization at connection points.
Data Source
AI summary
A method of compiling a verification system including a logic system design and a test bench for verifying the logic system design includes: receiving a description of the verification system, parsing the description of the verification system using a first parser and a second parser to generate a first intermediate representation (IR) and a second IR, respectively; analyzing the first and second IRs to generate exchange information; optimizing at least one of the first IR or the second IR based on the exchange information; and generating a first implementable code and a second implementable code respectively based on the first and second IRs after the optimization, wherein the first and second IRs are related by a connection point, and the exchange information is associated with the connection point.