Unified Data Processing Accelerator for Network Encryption and Checksum

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Solution Overview

Problem

Existing data processing technologies face inefficiencies due to redundant processing of encryption/decryption, message authentication, and checksum operations for network communications, leading to increased processing time and reduced throughput.

Innovation Solution

A data processing apparatus with a hardware processing circuit that integrates encryption/decryption, message authentication, and checksum processing units, allowing these operations to be performed in parallel or sequential combinations, reducing overlapping data accesses and optimizing bus occupancy through unified data processing units and pipeline processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If encryption/decryption, message authentication, and checksum processing are performed by separate hardware processing circuits, then processing speed is improved, but processing efficiency deteriorates due to multiple redundant accesses to the same data

Engineering Contradiction:
Improveprocessing speedVSAvoidprocessing efficiency
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent combines multiple separate processing circuits (encryption/decryption, message authentication, checksum) into a single integrated data processing unit. This unified structure processes all three types of data simultaneously in one pass, eliminating the need for multiple separate accesses to the same data and thereby resolving the contradiction between individual processing speed and overall processing efficiency.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The data processing unit is designed with multi-functionality to perform encryption/decryption, message authentication, and checksum processing within a single circuit. This universal processor can handle multiple processing types concurrently, allowing the system to maintain high speed while improving efficiency by avoiding redundant data accesses.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If multiple types of processing are performed independently in separate layers, then each processing can be executed separately, but overlapping data reads and writes cause deterioration of processing efficiency

Engineering Contradiction:
Improveprocessing flexibilityVSAvoidprocessing efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent merges multiple independent processing layers into a single integrated data processing unit that handles encryption/decryption, message authentication, and checksum processing simultaneously. This combination eliminates overlapping data accesses while maintaining the versatility to perform different processing types as needed.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The unified data processing unit enables continuous processing by reading data once and performing all necessary processing operations in sequence without interruption or redundant accesses. This continuous action eliminates the inefficiencies caused by separate layer processing while maintaining adaptability for different processing requirements.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS8918646B2Data processing apparatus
Publication Date: 2014.12.23 RENESAS ELECTRONICS CORP
  • US8918646B2 patent drawing
  • US8918646B2 patent drawing
  • US8918646B2 patent drawing

AI summary

In the configuration performing a data processing by a hardware processing circuit (accelerator), to provide a technology capable of improving a poorness of processing efficiency by multiple accesses to the data, the following solving means are provided. A network data processing accelerator of the present network data processing apparatus comprises processing units corresponding to each processing of an encryption/decryption, a message authentication, and a checksum, and in the data processing including a combination of each processing, accesses for the same data of the memory and the like through a bus I/F unit and the like is collected together into one time, and a pipeline processing is performed using the least common multiple of the data processing unit of each processing.