Unified DSP Module for Simultaneous Time and Frequency Domain Processing

Solution Overview

Problem

Prior digital signal processing systems are limited as they can only perform either block-based or sample-by-sample processing, not both simultaneously, leading to latency and overhead penalties when converting between algorithms.

Innovation Solution

A digital signal processor module that enables simultaneous processing of both sample-by-sample and block-based algorithms in a unified engine using shared memory and interrupt synchronization, allowing for dynamic allocation of software effects and low-latency processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If block-based algorithms are used for frequency domain processing, then computational flexibility is improved, but processing latency increases due to data accumulation requirements

Engineering Contradiction:

Improvecomputational flexibilityVSAvoidprocessing latency

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The processing engine is segmented into distinct block-based processing pathways and sample-by-sample processing pathways, allowing each to operate independently on different data streams or different time periods, thus resolving the latency-flexibility tradeoff by separating their operational requirements

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A single processing engine is designed to perform both block-based frequency domain processing and sample-by-sample time domain processing through unified data paths and control logic, enabling the system to switch between modes or execute both simultaneously without requiring separate hardware engines

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Loss of time

If sample-by-sample algorithms are used for processing, then processing latency is reduced, but computational flexibility is limited

Engineering Contradiction:

Improveprocessing latencyVSAvoidcomputational flexibility

Core Design Contradiction:

Loss of timeVSAdaptability or versatility

Solution Approach 1:

The processing engine is segmented into distinct block-based processing pathways and sample-by-sample processing pathways, allowing each to operate independently on different data streams or different time periods, thus resolving the latency-flexibility tradeoff by separating their operational requirements

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A single processing engine is designed to perform both block-based frequency domain processing and sample-by-sample time domain processing through unified data paths and control logic, enabling the system to switch between modes or execute both simultaneously without requiring separate hardware engines

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Productivity

If separate engines are used for SS and BB algorithms, then processing capability is improved, but device complexity increases

Engineering Contradiction:

Improveprocessing capabilityVSAvoidsystem complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent merges separate sample-by-sample and block-based processing engines into a single unified processing engine that shares common hardware resources including data paths, arithmetic logic units, and memory interfaces, thereby maintaining full processing capability while reducing overall device complexity

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

A single processing engine is designed to perform both block-based frequency domain processing and sample-by-sample time domain processing through unified data paths and control logic, enabling the system to switch between modes or execute both simultaneously without requiring separate hardware engines

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS7457484B2Method and device to process digital media streams

Publication Date: 2008.11.25 CREATIVE TECHNOLOGY LTD

AI summary

A method and digital processor to process digital samples is provided. The processor may comprise a time domain processing engine to process a digital sample in the time domain, and a frequency domain processing engine to process a digital sample in the frequency domain. Shared memory is provided in the digital processor with which time domain and frequency domain processed samples are exchangeable. The time domain processing engine may processes data samples in a sample-by-sample manner and the frequency domain processing engine may processes data samples in a block-based manner. The processing engines may be integrated in a single DSP chip. In one embodiment, an interrupt generator is provided that generates an interrupt and an input buffer communicates an input data sample to the processor in response to the interrupt and the output buffer communicates an output data sample to the digital sample bus in response to the interrupt.