Unified ECC Encoding Circuit for Multi-Type Memory
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Solution Overview
Problem
Current data error correction technologies require different error correction code (ECC) encoding circuits for various memory devices and types, leading to complexity and increased deployment costs, especially in chip shortages.
Innovation Solution
A data writing method that determines the codeword length based on the redundancy ratio of each memory type, allowing for ECC encoding without needing separate ECC encoding circuits for each memory type, thereby reducing complexity and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different ECC encoding circuits are deployed for each memory device and memory type, then data error correction reliability is improved, but device complexity and deployment costs increase
Solution Approach 1:
The patent implements a universal ECC encoding circuit that can handle multiple memory types (DDR4, DDR5, HBM) through a unified redundancy ratio configuration mechanism. The memory controller determines the appropriate redundancy ratio based on memory type and configures the same physical circuit accordingly, eliminating the need for separate dedicated ECC circuits for each memory type while maintaining data error correction reliability across all memory types
Solution Approach 2:
The patent changes the operational parameters (codeword length, redundancy ratio) of a single ECC encoding circuit based on the memory type being accessed. The memory controller dynamically adjusts these parameters according to the target memory device characteristics, allowing the same circuit to adapt to different memory types without requiring hardware changes, thus reducing device complexity while preserving reliability
2Reliability
If separate ECC encoding circuits are deployed for each memory type, then error correction performance is optimized for each memory type, but deployment costs increase
Solution Approach 1:
The patent creates a single deployable ECC encoding circuit that serves multiple memory types through configurable redundancy ratios. This universal approach reduces manufacturing and deployment costs by eliminating the need to produce, test, and maintain separate ECC circuit variants for different memory types, while still achieving optimized error correction performance for each specific memory type through parameter configuration
3Device complexity
If a single ECC encoding circuit is used for all memory types, then device complexity and deployment costs are reduced, but adaptability to different memory types may be compromised
Solution Approach 1:
The patent introduces dynamic configurability to the ECC encoding circuit through the memory controller, which adjusts the redundancy ratio and codeword length parameters based on the target memory type. This dynamic adaptation mechanism allows a single static circuit design to achieve versatile performance across different memory types (DDR4, DDR5, HBM) without compromising adaptability, while maintaining low device complexity
Solution Approach 2:
The system employs feedback through the memory controller that identifies the target memory type and accordingly configures the ECC encoding parameters before data writing. This feedback loop ensures the single ECC circuit is properly adapted to the specific memory type being accessed, maintaining full versatility while avoiding the complexity of multiple dedicated circuits
Data Source
AI summary
A data writing method includes obtaining first to-be-written data, where the first to-be-written data is data to be written into a first memory in the processing system; determining a first codeword length based on a first redundancy ratio corresponding to the first memory; performing ECC encoding on the first to-be-written data based on the first codeword length, to obtain first redundant data, where the first redundancy ratio is equal to a ratio of a data bit included in the first to-be-written data to a redundant bit included in the first redundant data; obtaining a memory type of the first memory; and writing the first to-be-written data and the first redundant data into the first memory based on the memory type.