Unified Execution Graphs for Heterogeneous Processor Scheduling
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Solution Overview
Problem
Modern embedded systems face challenges in performing high-performance computing operations due to the need for different programming libraries and paradigms for various processor types, leading to complex task management and data sharing between sub-tasks across multiple processor architectures.
Innovation Solution
The implementation of a unified programming model using Compute Uniform Device Architecture (CUDA) and deep learning accelerators (DLAs) enables seamless execution of software instructions across multiple processor architectures, facilitating unified memory access and streamlined task execution through a single software stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple programming libraries and paradigms are used for different processor types, then each processor can be optimized for its specific capabilities, but the system complexity and difficulty of task management increase significantly
Solution Approach 1:
The patent implements a unified programming model that allows a single programming interface to control multiple types of processors (CPU, GPU, DLA, etc.). The execution graph framework provides universal task representation that can be scheduled across heterogeneous processors without requiring separate programming libraries for each processor type, thus reducing task management complexity while maintaining processor-specific optimization capabilities
2Productivity
If separate programming approaches are used for each processor architecture, then processor-specific performance can be maximized, but data sharing and synchronization between sub-tasks become more complex
Solution Approach 1:
The execution graph serves as an intermediary data structure that represents computational tasks and their dependencies in a processor-agnostic manner. The compiler uses this execution graph to automatically generate processor-specific code while preserving data sharing relationships, thus simplifying data sharing operations while maintaining optimized performance for each processor type
3Ease of operation
If a unified programming model is implemented across multiple processor architectures, then development simplicity and data sharing ease improve, but the ability to leverage processor-specific optimizations may be reduced
Solution Approach 1:
The patent segments the compilation process into distinct phases: high-level language compilation to intermediate representation, execution graph generation, and processor-specific code generation. This segmentation allows the unified programming model to maintain development simplicity while the backend compilation stages apply processor-specific optimizations through the execution graph framework
Data Source
AI summary
Apparatuses, systems, and techniques to perform multi-architecture execution graphs. In at least one embodiment, a parallel processing platform, such as compute uniform device architecture (CUDA) generates multi-architecture execution graphs comprising a plurality of software kernels to be performed by one or more processor cores having one or more processor architectures.