Unified FIFO Checksum Insertion for UDP Data Block Transmission
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Solution Overview
Problem
Conventional circuits implementing the UDP standard require separate FIFOs for checksum calculation and insertion, leading to inefficient use of logic resources due to the need for additional RAM and state machines, especially in programmable logic devices where efficient logic use is crucial.
Innovation Solution
A circuit and method utilizing a combined FIFO/RAM memory array with a direct memory access circuit and an error detection circuit, allowing the checksum to be calculated and inserted at any location within the data stream without the need for separate FIFOs, by using a partitioned memory with a write address controller and selection circuit to replace dummy values with error detection values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If separate FIFOs are used for checksum calculation and data transmission, then the checksum can be inserted at the beginning of the packet, but the circuitry required increases due to additional RAM and state machines
Solution Approach 1:
The patent combines the data FIFO and checksum FIFO into a single unified FIFO structure. The memory array serves both purposes by storing data at sequential addresses while allowing direct writing of the checksum to a predetermined address (address 0). This eliminates the need for separate FIFOs and reduces the overall circuitry required.
Solution Approach 2:
The unified FIFO structure serves multiple functions: it stores data from the data source, stores the checksum from the error detection circuit, and enables retrieval of both in the correct sequence. The same memory array and control logic handle both data and checksum operations, making the system more efficient.
2Reliability
If a separate FIFO is used to hold the checksum, then the checksum can be transmitted at the correct time, but the logic resources are used inefficiently requiring additional RAM and state machines
Solution Approach 1:
The patent merges the checksum storage function into the main data FIFO structure. By using a unified memory array with address 0 reserved for the checksum, the system achieves reliable checksum transmission timing without requiring separate RAM and state machines, thus reducing logic resource usage.
Solution Approach 2:
The checksum is calculated and written to address 0 of the unified FIFO in advance, before the data transmission begins. This preliminary action ensures the checksum is ready at the correct time for transmission at the beginning of the packet, maintaining reliable timing without additional complex control logic.
3Ease of operation
If the checksum is calculated before the packet is transmitted, then the checksum can be placed in the header, but the data in the checksum location will have already been sent
Solution Approach 1:
The system performs preliminary action by writing a dummy value to address 0 (the checksum location) before data transmission begins. This dummy value temporarily occupies the location but will be replaced by the actual checksum once calculated, preventing data loss while enabling early checksum placement in the header.
Solution Approach 2:
Instead of the conventional approach where data is written sequentially starting from address 0, the patent inverts the approach by reserving address 0 for the checksum and writing data starting from address 1. This allows the checksum to be placed in the header position while data is transmitted in the correct sequence without overwriting the checksum.
Data Source
AI summary
A circuit for transmitting a block of data is disclosed. The circuit comprises a memory array having a plurality of memory locations coupled to receive data; a first data source coupled to the memory array, wherein data from the first data source is stored at sequential addressable memory locations of the plurality of memory locations on a first in, first out basis; a second data source coupled to the memory array, the second data source providing data to be stored in a predetermined memory location of the sequential addressable memory locations storing data from the second data source; and a selection circuit coupled to the first data source and the second data source for selecting data to be stored in the plurality of memory locations.