Unified Floating Point Check Procedure for Rounding Error Detection
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Solution Overview
Problem
Existing floating-point operation methods face delays and complexity in error detection and correction due to the need for separate check procedures for different rounding modes and normal/subnormal results, which increases hardware size and processing time.
Innovation Solution
A unified check procedure using bits of the unrounded proposed mantissa result is implemented, determining a check parameter to decide whether the rounded result needs incrementation, thereby reducing the number of functions and shifting operations, and allowing earlier detection of errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate check procedures are implemented for different rounding modes and normal/subnormal results, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent implements a unified check procedure that handles all rounding modes (round-to-nearest, round-toward-zero, round-toward-plus-infinity, round-toward-minus-infinity) and both normal and subnormal results through a single algorithm. The procedure uses the unrounded proposed mantissa result bits directly to determine a check parameter that indicates whether the rounded result is correct or needs incrementation, eliminating the need for separate check procedures for each rounding mode and result type.
2Reliability
If separate check procedures are implemented for different rounding modes and normal/subnormal results, then reliability is improved, but device complexity increases
Solution Approach 1:
The unified check procedure ensures reliable error detection across all rounding modes and result types by using a single consistent algorithm. The check parameter determination logic reliably identifies whether the rounded proposed mantissa result needs incrementation regardless of the rounding mode or whether the result is normal or subnormal, maintaining high reliability while reducing complexity.
3Manufacturing precision
If variable shifting operations are performed in check procedures, then manufacturing precision is improved, but loss of time increases
Solution Approach 1:
The patent determines the check parameter using bits from the unrounded proposed mantissa result before rounding occurs. By using the unrounded result bits directly in the check parameter determination logic, the procedure eliminates the need for variable shifting operations that would otherwise be required to align bits for subnormal results or different rounding modes, significantly reducing processing time while maintaining precision.
4Measurement precision
If multiple functions are implemented for different rounding modes and result types, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent consolidates multiple separate check procedure functions into a single unified function that handles all rounding modes and result types. The unified procedure uses a consistent logic to determine the check parameter from the unrounded proposed mantissa result, eliminating the need for separate functions for round-to-nearest, round-toward-zero, round-toward-plus-infinity, round-toward-minus-infinity, and for handling both normal and subnormal results separately.
Data Source
AI summary
Method and computer system for implementing an operation on ≥1 floating point input, in accordance with a rounding mode, e.g. using a Newton-Raphson technique. The floating point result comprises a p-bit mantissa. An unrounded proposed mantissa result is determined using the Newton-Raphson technique, wherein a p-bit rounded proposed mantissa result, t, corresponds to a rounding of the unrounded proposed mantissa result in accordance with the rounding mode, with k leading zeroes. If an increment to the (m−k)th bit of the unrounded result would affect the p-bit rounded result then the input(s) and bits of the unrounded result are used to determine a check parameter which is indicative of a relationship between an exact result and the unrounded result if the (m−k)th bit were incremented. The p-bit mantissa of the floating point result, is determined in dependence upon the check parameter, to be either t or t+1.