Unified Floating-Point Pipeline for RCP, SQRT, EXP, LOG Functions
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Solution Overview
Problem
Existing graphics processor chips require large gate counts and numerous data look-up tables to implement mathematical functions like reciprocal, square root, exponential, and logarithmic functions, which are inefficient for high-speed and mobile applications demanding lower power consumption and higher integration.
Innovation Solution
Implementing these functions using unified hardware circuitry with fewer than 1000 entries, employing quadratic approximations and shared data look-up tables, allowing for efficient computation of RCP, SQRT, EXP, and LOG functions through a single pipeline with floating-point to fixed-point conversions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate circuitry blocks with different algorithms are used for each mathematical function, then functional accuracy is maintained, but device complexity and gate count increase significantly
Solution Approach 1:
The patent implements a unified hardware pipeline that can perform multiple mathematical functions (RCP, SQRT, EXP, LOG) using a single set of circuitry blocks. The same pipeline stages and data look-up tables are reused across different functions, eliminating the need for separate dedicated circuits for each function while maintaining computational accuracy through function-specific algorithms and coefficients.
2Manufacturing precision
If large data look-up tables with over 16,000 entries are used to achieve required precision, then manufacturing precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent segments the input mantissa into two parts: a most significant bits (MSB) portion used to index into compact data look-up tables, and a least significant bits (LSB) portion used in subsequent calculation stages. This segmentation allows the use of small look-up tables (with far fewer than 16,000 entries) while still achieving the required precision through combined computation of both input portions.
Solution Approach 2:
The patent performs preliminary classification of input values by examining the MSB portion and determining which of several ranges the input falls into. Based on this preliminary classification, the system selects appropriate pre-computed coefficients and calculation procedures from the look-up tables, enabling high precision with reduced table sizes by preparing the computation path in advance.
3Adaptability or versatility
If multiple separate circuitry blocks are implemented for different mathematical functions, then functional versatility is maintained, but power consumption and area increase
Solution Approach 1:
The patent merges the implementation of multiple mathematical functions into a single unified hardware pipeline. The same computational stages, data look-up tables, and control logic are shared across RCP, SQRT, EXP, and LOG functions. This consolidation reduces the total hardware area and power consumption compared to having separate dedicated circuits for each function, while maintaining full functional versatility through software-controlled function selection.
Data Source
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AI summary
Methods and apparatus are provided for computing mathematical functions comprising a single pipeline for performing a polynomial approximation (e.g. a quadratic polynomial approximation, or the like), and one or more data tables corresponding to at least one of the RCP, SQRT, EXP or LOG functions operable to be coupled to the single pipeline according to one or more opcodes, wherein the single pipeline is operable for computing at least one of RCP, SQRT, EXP or LOG functions according to the one or more opcodes.