Unified FPGA View for Dynamic Resource Composition
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Solution Overview
Problem
In data centers, the conventional approach to resource management leads to inefficient utilization of resources due to over-allocation, resulting in higher total cost of ownership and lower return on investment, especially when managing compute, storage, and network resources.
Innovation Solution
The implementation of Rack Scale Design (RSD) with mechanisms for FPGA chaining and unified FPGA views allows for the enumeration and sharing of FPGA resources across compute nodes, enabling dynamic composition of resources based on workload demands and efficient utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional resource allocation is used in data centers, then resource availability is ensured, but resource utilization efficiency deteriorates due to over-allocation
Solution Approach 1:
The patent segments FPGA resources from individual compute nodes into a shared pool that can be dynamically allocated. Instead of dedicating FPGAs to specific compute nodes, the system divides and redistributes these resources across multiple nodes based on actual workload demands, thereby improving utilization efficiency while reducing over-allocation.
Solution Approach 2:
The system implements dynamic resource allocation where FPGA resources can be reassigned in real-time based on changing workload requirements. The resource manager continuously monitors utilization and reallocates FPGAs from underutilized compute nodes to those with higher demands, making the resource allocation flexible and adaptive rather than static.
2Reliability
If FPGA resources are dedicated to individual compute nodes, then resource availability is guaranteed, but overall system resource efficiency deteriorates
Solution Approach 1:
The patent makes FPGA resources universal by creating a shared pool that can serve multiple compute nodes. Instead of dedicating FPGAs to single nodes, the same FPGA resources can be allocated to different compute nodes depending on which workload requires them, enabling multi-functionality and improving overall system efficiency while maintaining availability through on-demand allocation.
Solution Approach 2:
The system implements self-service resource allocation where the resource manager automatically monitors FPGA utilization across compute nodes and reallocates resources without manual intervention. When a compute node has idle FPGAs and another node needs them, the system autonomously transfers ownership and configuration, ensuring continuous availability while optimizing efficiency.
3Adaptability or versatility
If static resource allocation is used, then system complexity is reduced, but adaptability to changing workload demands deteriorates
Solution Approach 1:
The patent implements feedback mechanisms where the resource manager continuously monitors FPGA utilization metrics across compute nodes and uses this information to make real-time allocation decisions. The system receives feedback on resource usage patterns and dynamically adjusts allocations to match actual workload demands, enabling high adaptability through data-driven resource management.
Solution Approach 2:
The resource manager acts as an intermediary layer between physical FPGA resources and compute nodes. This intermediary abstracts the complexity of direct resource management by handling allocation, deallocation, and reconfiguration tasks, thereby reducing the complexity burden on individual compute nodes while enabling sophisticated adaptive resource sharing across the system.
Data Source
AI summary
Mechanisms for Field Programmable Gate Array (FPGA) chaining and unified FPGA views to a composed system hosts and associated methods, apparatus, systems and software A rack is populated with pooled system drawers including pooled compute drawers and pooled FPGA drawers communicatively coupled via input-output (IO) cables. The FPGA resources in the pooled system drawers are enumerated, identifying a location of type of each FPGA and whether it is a chainable FPGA. Intra-drawer chaining mechanisms are identified for the chainable FPGAs in each pooled compute and pooled FPGA drawer. Inter-drawer chaining mechanism are also identified for chaining FPGAs in separate pooled system drawers. The enumerated FPGA and chaining mechanism data is aggregated to generate a unified system view of the FPGA resources and their chaining mechanisms. Based on available compute nodes and FPGAs in the unified system view, new compute nodes are composed using chained FPGAs. The chained FPGAs are exposed to a hypervisor or operating system virtualization layer, or to an operating system hosted by the composed compute node as a virtual monolithic FPGA or multiple local FPGAs.