Unified Hardware Cryptographic Circuit for RSA and ECC Operations
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Solution Overview
Problem
Current cryptographic systems face inefficiencies in terms of latency and power consumption due to the use of general-purpose processing circuitry for cryptographic operations, particularly for long-lived RSA and elliptic curve cryptography keys, which also incur high costs in die area and require separate hardware for different operations.
Innovation Solution
A specialized dedicated hardware cryptographic circuit is developed, incorporating a 27x411-bit multiplication circuit and ECC hardware circuitry that performs public key cryptographic operations with reduced latency and power consumption, allowing for both RSA and ECC operations in the same circuitry, leveraging parallel combinatorial multiplication and modulus reduction techniques to achieve high-speed operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general-purpose processing circuitry is used for cryptographic operations, then implementation flexibility is maintained, but latency increases and power consumption rises
Solution Approach 1:
The hardware cryptographic circuit is designed to perform multiple cryptographic operations including RSA and elliptic curve cryptography (ECC) using a unified architecture. The circuit includes configurable components that can be programmed to execute different cryptographic algorithms, eliminating the need for separate dedicated hardware for each operation while maintaining high-speed performance.
Solution Approach 2:
The patent replaces general-purpose software-based cryptographic processing with specialized hardware circuitry. This substitution of mechanical/software systems with dedicated hardware architecture achieves significant latency reduction (24 times faster multiplication) and lower power consumption while maintaining cryptographic functionality.
2Speed
If separate hardware is used for different cryptographic operations, then operation speed improves, but die area increases and cost rises
Solution Approach 1:
A single hardware cryptographic circuit is designed to perform multiple cryptographic operations including RSA and elliptic curve cryptography (ECC) using a unified architecture. The circuit includes configurable components that can be programmed to execute different cryptographic algorithms, eliminating the need for separate dedicated hardware for each operation while maintaining high-speed performance.
Solution Approach 2:
The patent combines multiple cryptographic function implementations into a single integrated hardware circuit. By merging RSA and ECC operations along with multiplication and modulus reduction functions into one unified circuit block, the design achieves space efficiency while maintaining the speed benefits of dedicated hardware.
3Loss of time
If specialized hardware cryptographic circuit is used, then latency is reduced and power consumption decreases, but device complexity increases
Solution Approach 1:
The hardware cryptographic circuit is divided into functional modules including multiplication units, modulus reduction circuits, and configurable processing blocks. This segmentation allows each component to be optimized for its specific function while working together in a coordinated manner, managing complexity through modular design.
Solution Approach 2:
The circuit incorporates configurable and programmable elements that allow the hardware to adapt its operation dynamically based on the specific cryptographic algorithm being executed. This dynamic capability enables a single circuit to perform multiple functions without requiring separate dedicated hardware for each operation.
Data Source
AI summary
In one embodiment, an apparatus includes a hardware accelerator to execute cryptography operations including a Rivest Shamir Adleman (RSA) operation and an elliptic curve cryptography (ECC) operation. The hardware accelerator may include a multiplier circuit comprising a parallel combinatorial multiplier, and an ECC circuit coupled to the multiplier circuit to execute the ECC operation. The ECC circuit may compute a prime field multiplication using the multiplier circuit and reduce a result of the prime field multiplication in a plurality of addition and subtraction operations for a first type of prime modulus. The hardware accelerator may execute the RSA operation using the multiplier circuit. Other embodiments are described and claimed.