Unified Hypervisor for Multi-Device Virtual Memory Mapping

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Solution Overview

Problem

Current computing systems face increased overhead and latency due to the serial coordination of virtual machines across different devices, particularly when accessing and processing data between hypervisors, which limits efficient utilization of multiple virtual machines.

Innovation Solution

A unified system map is created that maps virtual memory addresses across multiple physical devices, enabling cache-coherent access and reducing the need for PCIe and DMA transactions by allowing direct memory access between virtual machines, thereby facilitating efficient data transfer and processing across different physical devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If virtual machines are distributed across multiple devices with separate hypervisors, then computing resources are utilized more efficiently, but coordination overhead and latency increase due to serial operations

Engineering Contradiction:
Improvecomputing resource utilizationVSAvoidcoordination latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent merges multiple separate hypervisors into a single unified hypervisor that manages virtual machines across multiple devices. This consolidation eliminates the need for inter-hypervisor coordination protocols and allows direct memory access between VMs on different devices, reducing latency while maintaining efficient resource utilization.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The unified hypervisor serves multiple functions: it manages virtual machines on different device types (GPU, CPU, DPU), provides a common memory address space, and handles data transfer between VMs without requiring device-specific coordination protocols. This multi-functionality reduces overhead while supporting diverse computing resources.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Ease of operation

If PCIe and DMA transactions are used for data transfer between virtual machines on different devices, then data can be transferred between devices, but transaction overhead increases

Engineering Contradiction:
Improvedata transfer capabilityVSAvoidtransaction overhead
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent extracts the memory management and data transfer control functions from the device level and consolidates them at the unified hypervisor level. This allows VMs to access memory directly through the unified address space without requiring PCIe transactions or DMA setup, eliminating the complexity of device-level data transfer protocols while maintaining full data transfer capability.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If serial coordination is used between hypervisors, then data transfer between virtual machines on different devices is enabled, but computing overhead increases

Engineering Contradiction:
Improvedata transfer reliabilityVSAvoidcomputing overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

By merging multiple hypervisors into one unified hypervisor, the patent eliminates the need for serial coordination between separate hypervisor instances. The unified hypervisor provides a common memory management interface and direct access paths, maintaining reliable data transfer while removing the computational overhead associated with inter-hypervisor communication and coordination protocols.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11892946B2Disaggregated hypervisor on multiple devices
Publication Date: 2024.02.06 NVIDIA CORP
  • US11892946B2 patent drawing
  • US11892946B2 patent drawing
  • US11892946B2 patent drawing

AI summary

Apparatuses, systems, and techniques to allocate portions of a virtual address space to allow virtual machines to share data. In at least one embodiment, at least a portion of a virtual memory address space is made accessible to multiple virtual machines and is mapped to memory addresses of different physical devices using, at least in part, a cache-coherent protocol.