Unified IBIS Model Generation for Multi-Chip Module Pin Groups
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Solution Overview
Problem
Existing behavioral-modeling standards, such as IBIS, do not provide a satisfactory methodology for modeling and simulating multi-chip modules (MCMs), leading to impractically slow and complex simulations due to the complexity of detailed SPICE models and proprietary component information.
Innovation Solution
A method for generating unified behavioral models for pin groups in MCMs by identifying pin groups with multiple buffers connected to package-external pins and adjusting model data to account for the characteristics of each buffer, allowing for faster and more practical simulation of interconnected chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If detailed SPICE models are used for simulating interconnected chips in MCMs, then simulation accuracy is improved, but simulation time and complexity become impractically slow and unwieldy
Solution Approach 1:
The patent segments the complex SPICE model into two distinct models: a behavioral model that captures essential electrical characteristics (I/V curves, rise/fall times) for fast simulation, and a simplified RC extraction model that represents the interconnect wiring. This segmentation allows each model to be optimized for its specific purpose, resolving the contradiction between accuracy and speed.
Solution Approach 2:
The patent introduces an intermediary RC extraction model that acts as a mediator between the detailed SPICE model and the behavioral model. This intermediary model captures the essential wiring effects without the full complexity of the original SPICE model, enabling accurate yet fast simulation of MCM interconnects.
2Measurement precision
If detailed SPICE models are used for simulating interconnected chips, then simulation accuracy is improved, but device complexity and unwieldiness increase
Solution Approach 1:
The patent divides the modeling complexity into separate components: a behavioral model with simplified parameters (I/V curves, rise/fall times) and an RC extraction model for interconnects. This segmentation reduces the overall model complexity while preserving accuracy by allowing each component to be optimized independently.
Solution Approach 2:
The patent extracts only the essential characteristics from the detailed SPICE model—specifically the I/V curves, rise and fall times, and RC parameters—to create the behavioral model. This extraction process removes unnecessary complexity while retaining the critical information needed for accurate simulation.
3Productivity
If behavioral models are used instead of SPICE models, then simulation speed is improved, but the ability to model complex buffer interactions in pin groups is reduced
Solution Approach 1:
The patent merges multiple behavioral models representing individual buffers connected to the same pin group into a single unified behavioral model. This merging process combines the I/V curves, rise/fall times, and RC parameters of all buffers in the group, enabling the model to accurately represent the collective behavior of multiple buffers while maintaining fast simulation performance.
Solution Approach 2:
The unified behavioral model serves multiple functions: it represents the electrical characteristics of individual buffers, captures the interactions between multiple buffers in a pin group, and models the interconnect wiring effects. This multi-functionality allows a single model structure to handle complex buffer interactions without sacrificing simulation speed.
Data Source
AI summary
In one embodiment, the invention is a method for modeling electrical behavior of a packaged module having multiple integrated circuits (ICs), such as a multi-chip module (MCM). The method includes: (a) identifying one or more pin groups in the module, wherein a pin group comprises two or more buffers connected together and to a package-external pin, and (b) generating one or more corresponding unified behavioral models for the one or more pin groups based on the characteristics of the buffers of the one or more pin groups. The behavioral models are part of an integrated behavioral model file in accordance with the I/O buffer information specification (IBIS) standard.