Unified IDCT Microcode Processor Engine for Multi-Standard Video

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Solution Overview

Problem

Current hardware-implemented IDCT processors are limited to processing a single video standard, resulting in poor portability and slow performance when attempting to adapt to different video encoding standards.

Innovation Solution

A unified IDCT microcode processor engine with a pipeline structure comprising a read unit, shift left units, an add unit, and a shift right unit, capable of processing multiple video standards through a set of generated instructions that accommodate various encoding standards like MPEG, MPEG-2, MPEG-4, H.264, and VC-1, with reserved bits for future flexibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a hardware implemented IDCT processor is used, then processing speed is improved, but adaptability to different video standards deteriorates

Engineering Contradiction:
Improveprocessing speedVSAvoidadaptability to different video standards
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The IDCT processor is designed with a unified architecture that can process multiple video standards (MPEG, MPEG-2, MPEG-4, H.264, VC-1) through a single hardware structure. The processor uses configurable parameters and unified computation pathways to adapt to different standards without requiring separate hardware implementations for each standard, thereby achieving both high speed and multi-standard support

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If a generic microprocessor is used to adapt different video standards, then adaptability is improved, but processing speed and power consumption deteriorate

Engineering Contradiction:
Improveadaptability to different video standardsVSAvoidprocessing speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent replaces the software-based generic microprocessor approach with a dedicated hardware IDCT processor implementation. This substitution leverages parallel processing capabilities and optimized hardware circuits to achieve high-speed processing while maintaining adaptability through configurable parameters, thereby resolving the speed limitation of generic microprocessors

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Adaptability or versatility

If a generic microprocessor is used to adapt different video standards, then adaptability is improved, but power consumption deteriorates

Engineering Contradiction:
Improveadaptability to different video standardsVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent substitutes the high-power generic microprocessor with a specialized hardware IDCT processor designed for efficient signal processing. This hardware implementation uses optimized circuits and parallel processing to reduce power consumption while maintaining the ability to handle multiple video standards, thereby resolving the power consumption issue

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS8126952B2Unified inverse discrete cosine transform (IDCT) microcode processor engine
Publication Date: 2012.02.28 NVIDIA CORP
  • US8126952B2 patent drawing
  • US8126952B2 patent drawing
  • US8126952B2 patent drawing

AI summary

The present invention provides a unified inverse discrete cosine transform (IDCT) microcode processor engine, which is able to process IDCT with different video standards and also achieves the processing speed requirement. The microcode processor engine comprises a read unit for reading input data; a shift left unit comprising: a first shift left block for left-shifting input data; and a second shift left block for left-shifting input data; an add unit for adding data output from the shift left unit; and a shift right unit for right-shifting data output from the add unit. The present invention also provides a system of inverse discrete cosine transform.