Unified Idle State Machine for SoC Interconnect Credit Management
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Solution Overview
Problem
The integration of diverse intellectual property blocks into a single system-on-chip (SoC) is complex due to varying requirements and design uniqueness, necessitating significant customization and re-design to accommodate interface and signaling needs, which increases design complexity and slows the development of advanced semiconductor devices.
Innovation Solution
A unified idle state machine (ISM) architecture that provides a common interface for credit initialization, active mode data exchange, and power management, implemented via agent-based and fabric-based state machines, simplifies on-die interconnect communications and ties together credit management, data transmission, and power gating into a single state machine.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If diverse IP blocks are integrated into a single SoC to meet varying market requirements, then functionality and versatility are improved, but design complexity increases due to varying interface and signaling requirements
Solution Approach 1:
The patent applies universality by creating a common idle state machine architecture that serves multiple IP blocks across different market segments (server, desktop, mobile, embedded). This unified state machine handles credit management, active state coordination, and idle state transitions for diverse interfaces including PCIe and PCI, eliminating the need for separate customization for each IP block type while maintaining compatibility with varying interface requirements.
2Reliability
If IP blocks are customized for specific interface requirements, then interface compatibility is improved, but development time increases due to re-design needs
Solution Approach 1:
The patent implements preliminary action by pre-defining a standardized idle state machine architecture that anticipates and accommodates various interface requirements (PCIe, PCI, and other protocols). This pre-established framework allows IP blocks to be integrated without time-consuming re-design, as the state machine already contains the necessary credit management and state transition logic for multiple interface types, enabling faster time-to-market while maintaining interface compatibility.
3Reliability
If protocol layer responsibilities are segmented across transaction layer, link layer, and physical layer, then protocol compliance is improved, but system complexity increases due to multiple state machines
Solution Approach 1:
The patent applies merging by consolidating the idle state machine functionality that spans across protocol layers (transaction layer credit management, link layer active/idle transitions, and physical layer power management) into a single unified state machine. This integration reduces system complexity by eliminating the need for separate state machines in each layer while maintaining full protocol compliance, as the unified state machine coordinates all layer responsibilities through a centralized control mechanism.
Data Source
AI summary
In one embodiment, the present invention includes method for entering a credit initialization state of an agent state machine of an agent coupled to a fabric to initialize credits in a transaction credit tracker of the fabric. This tracker tracks credits for transaction queues of a first channel of the agent for a given transaction type. The agent may then assert a credit initialization signal to cause credits to be stored in the transaction credit tracker corresponding to the number of the transaction queues of the first channel of the agent for the first transaction type. Other embodiments are described and claimed.