Unified Instruction Cache Queue for Multi-Core Processor Bottlenecks
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Solution Overview
Problem
Existing technologies for instruction caching in multi-core processors require numerous FIFOs and register sets, leading to cumbersome control and unnecessary resource waste due to repeated information caching, which results in increased hardware costs and delays.
Innovation Solution
A caching device with a new structure that includes two queues and specific port configurations to efficiently manage missing instruction identifiers, allowing simultaneous storage of unresponded and unwrite-back instruction identifiers, reducing the need for multiple caching devices and register sets, and optimizing storage and processing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple FIFOs and register sets are used to cache missing instruction identifiers, then the function of fetching missing instructions is realized, but the device complexity increases and hardware resources are wasted
Solution Approach 1:
The patent merges multiple FIFOs and register sets into a single unified queue structure. Instead of using separate FIFOs for different stages (fetch, respond, write-back) and register sets for tracking, the invention uses one queue to store all missing instruction identifiers with associated stage information, significantly reducing hardware complexity while maintaining the complete missing instruction fetching function
Solution Approach 2:
The unified queue structure serves multiple functions simultaneously: it tracks missing instruction identifiers, monitors their processing stages (fetch, respond, write-back), and manages the complete lifecycle of missing instruction handling. This multi-functional design eliminates the need for separate dedicated structures for each function, reducing overall device complexity
2Reliability
If multiple FIFOs and register sets are used to cache missing instruction identifiers, then the missing instruction fetching function is realized, but hardware resources are wasted due to repeated information caching
Solution Approach 1:
The patent combines multiple separate hardware structures (FIFOs for different stages and register sets for tracking) into a single unified queue. This consolidation eliminates redundant storage of missing instruction identifiers across multiple structures, reducing hardware resource consumption while preserving the complete missing instruction fetching functionality
Solution Approach 2:
The unified queue uses different data bits within the same structure to represent different stages (fetch, respond, write-back) of missing instruction identifiers. This local differentiation within a unified structure allows the system to track multiple stages without requiring separate hardware structures for each stage, thereby reducing overall hardware resources
3Device complexity
If a unified queue structure with pop-up ports is used to cache missing instruction identifiers, then hardware costs are reduced, but the system must manage simultaneous operations on the same queue
Solution Approach 1:
The patent segments the queue operations by implementing different pop-up ports (first pop-up port for fetch stage, second pop-up port for write-back stage) that operate on specific portions or conditions of the queue data. This segmentation allows simultaneous operations to be managed systematically, reducing operational complexity despite the unified structure
Solution Approach 2:
The unified queue acts as an intermediary structure that mediates between different processing stages. The pop-up ports serve as controlled access points that manage simultaneous operations by directing them to appropriate data within the queue, simplifying the management of concurrent operations through a centralized coordination mechanism
Data Source
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AI summary
Instruction cache (210) comprises two caching devices (211, 212). Each caching device includes a first queue, a second queue, a write port group, a read port, a first pop-up port, a second pop-up port and a press-in port. The write port group is configured to write cache data into a set storage address in the first queue and/or the second queue; the read port is configured to read all cache data from the first queue and/or the second queue at one time; the press-in port is configured to press cache data into the first queue and/or the second queue; the first pop-up port is configured to pop up cache data from the first queue; and the second pop-up port is configured to pop up cache data from the second queue.